/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <bidram.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/param.h>
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#include <asm/arch/rk_atags.h>
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#include <asm/arch/sdram.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PARAM_DRAM_INFO_OFFSET 0x2000000
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#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
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size_t rockchip_sdram_size(phys_addr_t reg)
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{
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u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
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size_t chipsize_mb = 0;
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size_t size_mb = 0;
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u32 ch;
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u32 cs1_col = 0;
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u32 bg = 0;
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u32 dbw, dram_type;
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u32 sys_reg = readl(reg);
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u32 sys_reg1 = readl(reg + 4);
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u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
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& SYS_REG_NUM_CH_MASK);
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dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
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for (ch = 0; ch < ch_num; ch++) {
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rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
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SYS_REG_RANK_MASK);
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cs0_col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
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cs1_col = cs0_col;
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bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
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if ((sys_reg1 >> SYS_REG1_VERSION_SHIFT &
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SYS_REG1_VERSION_MASK) == 0x2) {
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cs1_col = 9 + (sys_reg1 >> SYS_REG1_CS1_COL_SHIFT(ch) &
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SYS_REG1_CS1_COL_MASK);
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if (((sys_reg1 >> SYS_REG1_EXTEND_CS0_ROW_SHIFT(ch) &
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SYS_REG1_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg >>
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK) == 7)
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cs0_row = 12;
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else
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cs0_row = 13 + (sys_reg >>
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SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK) +
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((sys_reg1 >>
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SYS_REG1_EXTEND_CS0_ROW_SHIFT(ch) &
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SYS_REG1_EXTEND_CS0_ROW_MASK) << 2);
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if (((sys_reg1 >> SYS_REG1_EXTEND_CS1_ROW_SHIFT(ch) &
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SYS_REG1_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg >>
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK) == 7)
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cs1_row = 12;
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else
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cs1_row = 13 + (sys_reg >>
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SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK) +
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((sys_reg1 >>
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SYS_REG1_EXTEND_CS1_ROW_SHIFT(ch) &
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SYS_REG1_EXTEND_CS1_ROW_MASK) << 2);
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}
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else {
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cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK);
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cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK);
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}
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bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
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SYS_REG_BW_MASK));
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row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
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SYS_REG_ROW_3_4_MASK;
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if (dram_type == DDR4) {
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dbw = (sys_reg >> SYS_REG_DBW_SHIFT(ch)) &
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SYS_REG_DBW_MASK;
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bg = (dbw == 2) ? 2 : 1;
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}
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chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
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if (rank > 1)
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chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
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(cs0_col - cs1_col));
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if (row_3_4)
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chipsize_mb = chipsize_mb * 3 / 4;
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size_mb += chipsize_mb;
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if (rank > 1)
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debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
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cs1_row %d bw %d row_3_4 %d\n",
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rank, cs0_col, cs1_col, bk, cs0_row,
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cs1_row, bw, row_3_4);
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else
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debug("rank %d cs0_col %d bk %d cs0_row %d\
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bw %d row_3_4 %d\n",
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rank, cs0_col, bk, cs0_row,
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bw, row_3_4);
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}
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/* Handle 4GB size, or else size will be 0 after <<20 in 32bit system */
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if (size_mb > (SDRAM_MAX_SIZE >> 20))
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size_mb = (SDRAM_MAX_SIZE >> 20);
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return (size_t)size_mb << 20;
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}
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static unsigned int get_ddr_os_reg(void)
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{
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u32 os_reg = 0;
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#if defined(CONFIG_ROCKCHIP_PX30)
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os_reg = readl(0xff010208);
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#elif defined(CONFIG_ROCKCHIP_RK3328)
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os_reg = readl(0xff1005d0);
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#elif defined(CONFIG_ROCKCHIP_RK3399)
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os_reg = readl(0xff320308);
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#elif defined(CONFIG_ROCKCHIP_RK322X)
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os_reg = readl(0x110005d0);
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#elif defined(CONFIG_ROCKCHIP_RK3368)
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os_reg = readl(0xff738208);
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#elif defined(CONFIG_ROCKCHIP_RK3288)
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os_reg = readl(0x20004048);
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#elif defined(CONFIG_ROCKCHIP_RK3036)
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os_reg = readl(0x200081cc);
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#elif defined(CONFIG_ROCKCHIP_RK3308)
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os_reg = readl(0xff000508);
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#elif defined(CONFIG_ROCKCHIP_RK1808)
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os_reg = readl(0xfe020208);
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#else
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printf("unsupported chip type, get page size fail\n");
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#endif
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return os_reg;
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}
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unsigned int get_page_size(void)
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{
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u32 os_reg;
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u32 col, bw;
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int page_size;
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os_reg = get_ddr_os_reg();
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if (!os_reg)
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return 0;
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col = 9 + (os_reg >> SYS_REG_COL_SHIFT(0) & SYS_REG_COL_MASK);
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bw = (2 >> ((os_reg >> SYS_REG_BW_SHIFT(0)) & SYS_REG_BW_MASK));
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page_size = 1u << (col + bw);
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return page_size;
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}
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unsigned int get_ddr_bw(void)
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{
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u32 os_reg;
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u32 bw = 2;
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os_reg = get_ddr_os_reg();
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if (os_reg)
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bw = 2 >> ((os_reg >> SYS_REG_BW_SHIFT(0)) & SYS_REG_BW_MASK);
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return bw;
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}
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#if defined(CONFIG_SPL_FRAMEWORK) || !defined(CONFIG_SPL_OF_PLATDATA)
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int dram_init_banksize(void)
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{
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#ifdef CONFIG_BIDRAM
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bidram_gen_gd_bi_dram();
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#else
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param_simple_parse_ddr_mem(1);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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#ifdef CONFIG_BIDRAM
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gd->ram_size = bidram_get_ram_size();
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#else
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gd->ram_size = param_simple_parse_ddr_mem(0);
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#endif
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if (!gd->ram_size)
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return -ENOMEM;
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return 0;
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}
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#endif
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ulong board_get_usable_ram_top(ulong total_size)
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{
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unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
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return (gd->ram_top > top) ? top : gd->ram_top;
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}
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int rockchip_setup_ddr_param(struct ddr_param *info)
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{
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u32 i;
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struct ddr_param *dinfo = (struct ddr_param *)(CONFIG_SYS_SDRAM_BASE +
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PARAM_DRAM_INFO_OFFSET);
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dinfo->count = info->count;
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for (i = 0; i < (info->count * 2); i++)
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dinfo->para[i] = info->para[i];
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return 0;
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}
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