/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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* Author: Zhihuan He <huan.he@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <ram.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rv1108.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0x10300000
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void board_debug_uart_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rv1108_grf *grf = (void *)GRF_BASE;
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0x10230000)
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enum {
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GPIO3A6_SHIFT = 12,
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GPIO3A6_MASK = 3 << GPIO3A6_SHIFT,
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GPIO3A6_GPIO = 0,
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GPIO3A6_UART1_SOUT,
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GPIO3A5_SHIFT = 10,
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GPIO3A5_MASK = 3 << GPIO3A5_SHIFT,
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GPIO3A5_GPIO = 0,
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GPIO3A5_UART1_SIN,
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};
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rk_clrsetreg(&grf->gpio3a_iomux, /* UART0 */
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GPIO3A6_MASK | GPIO3A5_MASK,
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GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
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GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
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#else
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enum {
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GPIO2D2_SHIFT = 4,
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GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
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GPIO2D2_GPIO = 0,
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GPIO2D2_UART2_SOUT_M0,
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GPIO2D1_SHIFT = 2,
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GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART2_SIN_M0,
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};
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rk_clrsetreg(&grf->gpio2d_iomux, /* UART2 */
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GPIO2D2_MASK | GPIO2D1_MASK,
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GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
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GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
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#endif
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#endif /*CONFIG_SPL_BUILD*/
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}
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