// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Rockchip Electronics Co., Ltd
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*
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*/
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#include <common.h>
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#include <android_image.h>
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#include <boot_rkimg.h>
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#include <ramdisk.h>
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#include <asm/io.h>
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#include <asm/arch/grf_rk1808.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/rk_atags.h>
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#include <asm/arch/rockchip_smccc.h>
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#include <asm/gpio.h>
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#include <debug_uart.h>
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#include <asm/armv8/mmu.h>
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#define NIU_CIF_ADDR 0xfe8a0188
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#define NIU_ISP_ADDR 0xfe8a0008
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
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static struct mm_region rk1808_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xff000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk1808_mem_map;
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#define GRF_BASE 0xfe000000
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#define PMUGRF_BASE 0xfe020000
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enum {
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GPIO4A3_SHIFT = 12,
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GPIO4A3_MASK = GENMASK(15, 12),
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GPIO4A3_GPIO = 0,
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GPIO4A3_SDMMC0_D1,
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GPIO4A3_UART2_RX_M0,
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GPIO4A2_SHIFT = 8,
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GPIO4A2_MASK = GENMASK(11, 8),
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GPIO4A2_GPIO = 0,
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GPIO4A2_SDMMC0_D0,
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GPIO4A2_UART2_TX_M0,
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UART2_IO_SEL_SHIFT = 14,
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UART2_IO_SEL_MASK = GENMASK(15, 14),
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UART2_IO_SEL_M0 = 0,
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UART2_IO_SEL_M1,
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UART2_IO_SEL_M2,
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UART2_IO_SEL_USB,
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};
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#define SECURE_FIRE_WALL 0xff590040
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int arch_cpu_init(void)
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{
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/* Set cif qos priority */
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writel(QOS_PRIORITY_LEVEL(2, 2), NIU_CIF_ADDR);
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writel(QOS_PRIORITY_LEVEL(2, 2), NIU_ISP_ADDR);
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/* Set dram to unsecure */
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#ifdef CONFIG_SPL_BUILD
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writel(0, SECURE_FIRE_WALL);
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#endif
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return 0;
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}
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/*
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* Default use UART2_TX/RX_M0(TX: GPIO4_A2, RX: GPIO4_A3)
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*/
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void board_debug_uart_init(void)
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{
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#ifdef CONFIG_TPL_BUILD
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struct rk1808_grf * const grf = (void *)GRF_BASE;
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/* Enable early UART2 channel m0 on the rk1808 */
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rk_clrsetreg(&grf->iofunc_con0, UART2_IO_SEL_MASK,
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UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
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/* Switch iomux */
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rk_clrsetreg(&grf->gpio4a_iomux_l,
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GPIO4A3_MASK | GPIO4A2_MASK,
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GPIO4A2_UART2_TX_M0 << GPIO4A2_SHIFT |
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GPIO4A3_UART2_RX_M0 << GPIO4A3_SHIFT);
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#endif
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}
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#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_COPROCESSOR_RK1808)
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#define PINCTRL_EMMC_BUS8_PATH "/pinctrl/emmc/emmc-bus8"
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#define PINCTRL_EMMC_CMD_PATH "/pinctrl/emmc/emmc-cmd"
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#define PINCTRL_EMMC_CLK_PATH "/pinctrl/emmc/emmc-clk"
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#define PINCTRL_PCFG_PU_2MA_PATH "/pinctrl/pcfg-pull-up-2ma"
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#define MAX_ROCKCHIP_PINS_ENTRIES 12
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static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
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{
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u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
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const u32 *data;
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int i, count;
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int node;
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node = fdt_path_offset(gd->fdt_blob, path);
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if (node < 0) {
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debug("%s: can't find: %s\n", __func__, path);
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return node;
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}
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data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
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if (!data) {
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debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
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return -ENODATA;
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}
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count /= sizeof(u32);
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if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
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debug("%s: %d is over max count\n", __func__, count);
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return -EINVAL;
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}
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for (i = 0; i < count; i++)
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cells[i] = data[i];
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for (i = 0; i < (count >> 2); i++)
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cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
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fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
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&cells, count * sizeof(u32));
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return 0;
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}
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int rk_board_fdt_fixup(void *blob)
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{
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struct tag *t;
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u32 ph_pu_2ma;
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int ret = 0;
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t = atags_get_tag(ATAG_SOC_INFO);
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if (!t)
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return 0;
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debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
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if (t->u.soc.flags != 0x45543030)
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return 0;
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ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
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fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
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if (!ph_pu_2ma) {
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debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
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return -EINVAL;
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}
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ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
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ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
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ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
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return ret;
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}
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#endif
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/*
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* rockchip: rk1808: fixup "ramdisk_addr_r" by real image address
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*
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* We fixup "ramdisk_addr_r" with real image address which has been already
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* loaded by pre-loader. This brings benefits:
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*
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* - It saves boot time when ramdisk is large;
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* - It avoids memory overlap with original ramdisk data.
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*/
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#if defined(CONFIG_DM_RAMDISK) && !defined(CONFIG_SPL_BUILD)
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static int env_fixup_ramdisk_addr_r(void)
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{
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const char *boot_part = PART_BOOT;
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struct blk_desc *dev_desc;
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struct andr_img_hdr *hdr;
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disk_partition_t info;
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ulong ramdisk_addr_r;
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int ret;
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/*
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* Don't rely on CONFIG_DM_RAMDISK since it can be a default
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* configuration after disk/part_rkram.c was introduced.
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*
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* This is compatible code.
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*/
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if (!dm_ramdisk_is_enabled())
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return 0;
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dev_desc = rockchip_get_bootdev();
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if (!dev_desc) {
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printf("%s: dev_desc is NULL!\n", __func__);
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return -ENODEV;
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}
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ret = part_get_info_by_name(dev_desc, boot_part, &info);
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if (ret < 0) {
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printf("%s: failed to get %s part, ret=%d\n",
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__func__, boot_part, ret);
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}
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hdr = (struct andr_img_hdr *)(info.start * dev_desc->blksz);
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ramdisk_addr_r = (ulong)hdr;
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ramdisk_addr_r += hdr->page_size;
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ramdisk_addr_r += ALIGN(hdr->kernel_size, hdr->page_size);
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env_set_hex("ramdisk_addr_r", ramdisk_addr_r);
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return 0;
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}
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#endif
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int rk_board_init(void)
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{
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struct rk1808_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
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/* Set GPIO0_C2 default to pull down from normal */
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rk_clrsetreg(&pmugrf->gpio0c_p, 0x30, 0x20);
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#if defined(CONFIG_ROCKCHIP_SMCCC) && defined(CONFIG_ROCKCHIP_RK1806)
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sip_smc_get_sip_version();
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#endif
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return 0;
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}
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int rk_board_late_init(void)
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{
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#if defined(CONFIG_DM_RAMDISK) && !defined(CONFIG_SPL_BUILD)
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env_fixup_ramdisk_addr_r();
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#endif
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return 0;
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}
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void mmc_gpio_init_direct(void)
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{
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struct rk1808_grf * const grf = (void *)GRF_BASE;
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/*
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* The rk1808's pin drive strength control must set to 2ma.
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*/
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rk_clrsetreg(&grf->gpio1a_e, 0xffff, 0x5555);
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rk_clrsetreg(&grf->gpio1b_e, 0xff, 0x00);
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}
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