/*
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* Adaptive Body Bias programming sequence for OMAP family
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
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{
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return -1;
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}
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static void abb_setup_timings(u32 setup)
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{
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u32 sys_rate, sr2_cnt, clk_cycles;
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/*
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* SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
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* transition and must be programmed with the correct time at boot.
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* The value programmed into the register is the number of SYS_CLK
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* clock cycles that match a given wall time profiled for the ldo.
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* This value depends on:
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* settling time of ldo in micro-seconds (varies per OMAP family),
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* of clock cycles per SYS_CLK period (varies per OMAP family),
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* the SYS_CLK frequency in MHz (varies per board)
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* The formula is:
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*
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* ldo settling time (in micro-seconds)
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* SR2_WTCNT_VALUE = ------------------------------------------
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* (# system clock cycles) * (sys_clk period)
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*
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* Put another way:
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*
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* SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
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*
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* To avoid dividing by zero multiply both "# clock cycles" and
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* "settling time" by 10 such that the final result is the one we want.
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*/
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/* calculate SR2_WTCNT_VALUE */
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sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
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clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
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sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
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setbits_le32(setup,
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sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
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}
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void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
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u32 txdone, u32 txdone_mask, u32 opp)
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{
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u32 abb_type_mask, opp_sel_mask;
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/* sanity check */
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if (!setup || !control || !txdone)
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return;
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/* setup ABB only in case of Fast or Slow OPP */
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switch (opp) {
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case OMAP_ABB_FAST_OPP:
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abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
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opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
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break;
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case OMAP_ABB_SLOW_OPP:
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abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
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opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
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break;
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default:
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return;
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}
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/*
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* For some OMAP silicons additional setup for LDOVBB register is
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* required. This is determined by data retrieved from corresponding
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* OPP EFUSE register. Data, which is retrieved from EFUSE - is
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* ABB enable/disable flag and VSET value, which must be copied
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* to LDOVBB register. If function call fails - return quietly,
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* it means no ABB is required for such silicon.
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*
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* For silicons, which don't require LDOVBB setup "fuse" and
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* "ldovbb" offsets are not defined. ABB will be initialized in
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* the common way for them.
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*/
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if (fuse && ldovbb) {
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if (abb_setup_ldovbb(fuse, ldovbb))
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return;
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}
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/* clear ABB registers */
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writel(0, setup);
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writel(0, control);
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/* configure timings, based on oscillator value */
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abb_setup_timings(setup);
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/* clear pending interrupts before setup */
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setbits_le32(txdone, txdone_mask);
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/* select ABB type */
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setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
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/* initiate ABB ldo change */
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setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
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/* wait until transition complete */
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if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
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puts("Error: ABB txdone is not set\n");
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/* clear ABB tranxdone */
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setbits_le32(txdone, txdone_mask);
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}
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