/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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static void *base = (void *)IOMUXC_BASE_ADDR;
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/*
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* iomuxc0 base address. In imx7ulp-pins.h,
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* the offsets of pins in iomuxc0 are from 0xD000,
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* so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
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*/
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static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
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/*
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* configures a single pad in the iomuxer
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*/
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void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
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{
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u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 sel_input_ofs =
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(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 sel_input =
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(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 pad_ctrl_ofs = mux_ctrl_ofs;
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u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
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pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
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pad_ctrl_ofs, pad_ctrl);
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if (mux_mode & IOMUX_CONFIG_MPORTS) {
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mux_mode &= ~IOMUX_CONFIG_MPORTS;
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base = base_mports;
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} else {
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base = (void *)IOMUXC_BASE_ADDR;
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}
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__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
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IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
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if (sel_input_ofs)
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__raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
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base + sel_input_ofs);
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if (!(pad_ctrl & NO_PAD_CTRL))
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__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
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IOMUXC_PCR_MUX_ALT_MASK) |
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(pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
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base + pad_ctrl_ofs);
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}
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/* configures a list of pads within declared with IOMUX_PADS macro */
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void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
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unsigned count)
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{
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iomux_cfg_t const *p = pad_list;
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int i;
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for (i = 0; i < count; i++) {
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mx7ulp_iomux_setup_pad(*p);
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p++;
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}
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}
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