/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
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#error "CPU_TYPE not defined"
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#endif
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u32 get_cpu_rev(void)
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{
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#ifdef CONFIG_MX51
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int system_rev = 0x51000;
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#else
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int system_rev = 0x53000;
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#endif
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int reg = __raw_readl(ROM_SI_REV);
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#if defined(CONFIG_MX51)
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switch (reg) {
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case 0x02:
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system_rev |= CHIP_REV_1_1;
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break;
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case 0x10:
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if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
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system_rev |= CHIP_REV_2_5;
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else
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system_rev |= CHIP_REV_2_0;
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break;
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case 0x20:
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system_rev |= CHIP_REV_3_0;
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break;
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default:
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system_rev |= CHIP_REV_1_0;
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break;
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}
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#else
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if (reg < 0x20)
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system_rev |= CHIP_REV_1_0;
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else
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system_rev |= reg;
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#endif
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return system_rev;
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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return get_cpu_rev();
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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int i;
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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for (i = 0; i < 6; i++)
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mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
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}
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#endif
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#ifdef CONFIG_MX53
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void boot_mode_apply(unsigned cfg_val)
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{
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writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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*
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* If bit 28 of LPGR is set upon watchdog reset,
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* bits[25:0] of LPGR will move to SBMR.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
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/* usb or serial download */
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{"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
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{"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
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{"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
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{"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
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{"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
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{"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
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/* 4 bit bus width */
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{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
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{"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
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{"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
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{"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
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{NULL, 0},
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};
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#endif
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