/*
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* Copyright (C) 2004 Texas Instruments.
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* Copyright (C) 2009 David Brownell
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* offsets from PLL controller base */
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#define PLLC_PLLCTL 0x100
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#define PLLC_PLLM 0x110
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#define PLLC_PREDIV 0x114
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#define PLLC_PLLDIV1 0x118
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#define PLLC_PLLDIV2 0x11c
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#define PLLC_PLLDIV3 0x120
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#define PLLC_POSTDIV 0x128
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#define PLLC_BPDIV 0x12c
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#define PLLC_PLLDIV4 0x160
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#define PLLC_PLLDIV5 0x164
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#define PLLC_PLLDIV6 0x168
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#define PLLC_PLLDIV7 0x16c
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV9 0x174
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/* SOC-specific pll info */
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#ifdef CONFIG_SOC_DM355
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#define ARM_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DM644X
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV2
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#endif
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#ifdef CONFIG_SOC_DM646X
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DA8XX
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unsigned int sysdiv[9] = {
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PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
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PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
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};
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int clk_get(enum davinci_clk_ids id)
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{
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int pre_div;
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int pllm;
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int post_div;
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int pll_out;
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unsigned int pll_base;
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pll_out = CONFIG_SYS_OSCIN_FREQ;
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if (id == DAVINCI_AUXCLK_CLKID)
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goto out;
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if ((id >> 16) == 1)
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pll_base = (unsigned int)davinci_pllc1_regs;
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else
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pll_base = (unsigned int)davinci_pllc0_regs;
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id &= 0xFFFF;
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/*
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* Lets keep this simple. Combining operations can result in
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* unexpected approximations
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*/
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pre_div = (readl(pll_base + PLLC_PREDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pllm = readl(pll_base + PLLC_PLLM) + 1;
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pll_out /= pre_div;
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pll_out *= pllm;
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if (id == DAVINCI_PLLM_CLKID)
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goto out;
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post_div = (readl(pll_base + PLLC_POSTDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= post_div;
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if (id == DAVINCI_PLLC_CLKID)
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goto out;
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pll_out /= (readl(pll_base + sysdiv[id - 1]) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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out:
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return pll_out;
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}
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int set_cpu_clk_info(void)
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{
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gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
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/* DDR PHY uses an x2 input clock */
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gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
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(clk_get(DAVINCI_DDR_CLKID) / 1000000);
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#else /* CONFIG_SOC_DA8XX */
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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{
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u32 div;
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div = REG(pllbase + offset);
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return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
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}
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static inline unsigned pll_prediv(volatile void *pllbase)
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{
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#ifdef CONFIG_SOC_DM355
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/* this register read seems to fail on pll0 */
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return 8;
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else
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return pll_div(pllbase, PLLC_PREDIV);
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#elif defined(CONFIG_SOC_DM365)
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return pll_div(pllbase, PLLC_PREDIV);
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#endif
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return 1;
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}
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static inline unsigned pll_postdiv(volatile void *pllbase)
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{
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#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
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return pll_div(pllbase, PLLC_POSTDIV);
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#elif defined(CONFIG_SOC_DM6446)
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return pll_div(pllbase, PLLC_POSTDIV);
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#endif
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return 1;
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}
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static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
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{
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volatile void *pllbase = (volatile void *) pll_addr;
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#ifdef CONFIG_SOC_DM646X
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unsigned base = CONFIG_REFCLK_FREQ / 1000;
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#else
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unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
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#endif
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/* the PLL might be bypassed */
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if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
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base /= pll_prediv(pllbase);
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#if defined(CONFIG_SOC_DM365)
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base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
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#else
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base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
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#endif
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base /= pll_postdiv(pllbase);
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}
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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}
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#ifdef DAVINCI_DM6467EVM
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unsigned int davinci_arm_clk_get()
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{
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
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}
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#endif
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#if defined(CONFIG_SOC_DM365)
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unsigned int davinci_clk_get(unsigned int div)
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{
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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}
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#endif
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int set_cpu_clk_info(void)
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{
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unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#if defined(CONFIG_SOC_DM365)
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pllbase = DAVINCI_PLL_CNTRL1_BASE;
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#endif
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gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
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#ifdef DSP_PLLDIV
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gd->bd->bi_dsp_freq =
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
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#else
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gd->bd->bi_dsp_freq = 0;
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#endif
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pllbase = DAVINCI_PLL_CNTRL1_BASE;
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#if defined(CONFIG_SOC_DM365)
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pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#endif
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gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
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return 0;
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}
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#endif /* !CONFIG_SOC_DA8XX */
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_DRIVER_TI_EMAC)
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davinci_emac_initialize();
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#endif
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return 0;
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}
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