/*
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* (C) Copyright 2012 Stephen Warren
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/wdog.h>
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#include <efi_loader.h>
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#define RESET_TIMEOUT 10
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/*
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* The Raspberry Pi firmware uses the RSTS register to know which partiton
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* to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.
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* Partiton 63 is a special partition used by the firmware to indicate halt.
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*/
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#define BCM2835_WDOG_RSTS_RASPBERRYPI_HALT 0x555
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/* max ticks timeout */
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#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
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#ifdef CONFIG_BCM2835_WDT
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extern void hw_watchdog_disable(void);
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#else
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void hw_watchdog_disable(void) {}
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#endif
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__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
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(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
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void __efi_runtime reset_cpu(ulong ticks)
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{
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uint32_t rstc, timeout;
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if (ticks == 0) {
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hw_watchdog_disable();
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timeout = RESET_TIMEOUT;
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} else
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timeout = ticks & BCM2835_WDOG_MAX_TIMEOUT;
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rstc = readl(&wdog_regs->rstc);
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rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
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rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
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writel(BCM2835_WDOG_PASSWORD | timeout, &wdog_regs->wdog);
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writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
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}
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#ifdef CONFIG_EFI_LOADER
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void __efi_runtime EFIAPI efi_reset_system(
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enum efi_reset_type reset_type,
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efi_status_t reset_status,
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unsigned long data_size, void *reset_data)
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{
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u32 val;
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switch (reset_type) {
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case EFI_RESET_COLD:
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case EFI_RESET_WARM:
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reset_cpu(0);
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break;
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case EFI_RESET_SHUTDOWN:
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/*
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* We set the watchdog hard reset bit here to distinguish this reset
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* from the normal (full) reset. bootcode.bin will not reboot after a
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* hard reset.
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*/
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val = readl(&wdog_regs->rsts);
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val |= BCM2835_WDOG_PASSWORD;
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val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
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writel(val, &wdog_regs->rsts);
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reset_cpu(0);
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break;
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}
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while (1) { }
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}
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void efi_reset_system_init(void)
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{
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efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
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}
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#endif
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