/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2012
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* Markus Hubig <mhubig@imko.de>
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* IMKO GmbH <www.imko.de>
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*
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* Copyright (C) 2013 DENX Software Engineering, hs@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <asm/arch/at91_rstc.h>
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#include <watchdog.h>
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void at91_phy_reset(void)
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{
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unsigned long erstl;
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unsigned long start = get_timer(0);
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unsigned long const timeout = 1000; /* 1000ms */
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at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
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erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
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/*
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* Need to reset PHY -> 500ms reset
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* Reset PHY by pulling the NRST line for 500ms to low. To do so
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* disable user reset for low level on NRST pin and poll the NRST
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* level in reset status register.
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*/
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
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AT91_RSTC_MR_URSTEN, &rstc->mr);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
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/* Wait for end of hardware reset */
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while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
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/* avoid shutdown by watchdog */
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WATCHDOG_RESET();
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mdelay(10);
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/* timeout for not getting stuck in an endless loop */
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if (get_timer(start) >= timeout) {
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puts("*** ERROR: Timeout waiting for PHY reset!\n");
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break;
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}
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};
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/* Restore NRST value */
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writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
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}
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