/*
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* vectors - Generic ARM exception table code
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*
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* Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/*
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* A macro to allow insertion of an ARM exception vector either
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* for the non-boot0 case or by a boot0-header.
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*/
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.macro ARM_VECTORS
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b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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.endm
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/*
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*************************************************************************
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*
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* Symbol _start is referenced elsewhere, so make it global
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*
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*************************************************************************
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*/
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.globl _start
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/*
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*************************************************************************
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*
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* Vectors have their own section so linker script can map them easily
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*
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*************************************************************************
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*/
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.section ".vectors", "ax"
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#if defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
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/*
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* Various SoCs need something special and SoC-specific up front in
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* order to boot, allow them to set that in their boot0.h file and then
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* use it here.
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*
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* To allow a boot0 hook to insert a 'special' sequence after the vector
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* table (e.g. for the socfpga), the presence of a boot0 hook supresses
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* the below vector table and assumes that the vector table is filled in
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* by the boot0 hook. The requirements for a boot0 hook thus are:
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* (1) defines '_start:' as appropriate
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* (2) inserts the vector table using ARM_VECTORS as appropriate
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*/
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#include <asm/arch/boot0.h>
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#else
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/*
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*************************************************************************
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*
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* Exception vectors as described in ARM reference manuals
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*
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* Uses indirect branch to allow reaching handlers anywhere in memory.
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*
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*************************************************************************
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*/
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_start:
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#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
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.word CONFIG_SYS_DV_NOR_BOOT_CFG
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#endif
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ARM_VECTORS
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#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
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/*
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*************************************************************************
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*
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* Indirect vectors table
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*
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* Symbols referenced here must be defined somewhere else
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*
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*************************************************************************
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*/
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.globl _undefined_instruction
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.globl _software_interrupt
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.globl _prefetch_abort
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.globl _data_abort
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.globl _not_used
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.globl _irq
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.globl _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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/* SPL interrupt handling: just hang */
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#ifdef CONFIG_SPL_BUILD
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.align 5
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undefined_instruction:
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software_interrupt:
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prefetch_abort:
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data_abort:
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not_used:
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irq:
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fiq:
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1:
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bl 1b /* hang and never return */
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#else /* !CONFIG_SPL_BUILD */
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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#ifdef IRAM_BASE_ADDR
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.word IRAM_BASE_ADDR + 0x20
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#else
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.word 0x0badc0de
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#endif
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#if CONFIG_IS_ENABLED(IRQ)
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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#endif
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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@ carve out a frame on current user stack
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
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ldr r2, IRQ_STACK_START_IN
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@ get values for "aborted" pc and cpsr (into parm regs)
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ldmia r2, {r2 - r3}
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0 (param register)
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
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add r8, sp, #S_PC
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cps #MODE_SVC @ SVC-Mode
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isb
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mov r1, sp @ svc_sp
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mov r2, lr @ svc_lr
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cps #MODE_IRQ @ IRQ-Mode
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isb
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stmdb r8, {r1, r2}^ @ Calling svc_sp, svc_lr
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack
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str lr, [r13] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction & switch modes.
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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.align 5
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irq:
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#if CONFIG_IS_ENABLED(IRQ)
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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#else
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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#endif
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif /* CONFIG_SPL_BUILD */
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