/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/compiler.h>
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#include <efi_loader.h>
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#include <iomem.h>
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#include <stacktrace.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !CONFIG_IS_ENABLED(IRQ)
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int interrupt_init(void)
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{
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return 0;
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}
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void enable_interrupts(void)
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{
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return;
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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#endif
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#define REG_BITS(val, shift, mask) (((val) >> (shift)) & (mask))
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#ifndef CONFIG_SPL_BUILD
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void show_regs(struct pt_regs *regs)
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{
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int el = current_el();
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int i;
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const char *esr_bits_ec[] = {
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[0] = "an unknown reason",
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[1] = "a WFI or WFE instruction",
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[3] = "an MCR or MRC access",
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[4] = "an MCRR or MRRC access",
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[5] = "an MCR or MRC access",
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[6] = "an LDC or STC access to CP14",
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[7] = "an access to an Advanced SIMD or floating-point register, resulting from CPACR_EL1.FPEN or CPTR_ELx.TFP",
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[8] = "an MCR or MRC access",
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[12] = "an MCRR or MRRC access",
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[14] = "an Illegal execution state, or a PC or SP alignment fault",
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[10] = "HVC or SVC instruction execution",
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[18] = "HVC or SVC instruction execution",
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[19] = "SMC instruction execution in AArch32 state",
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[21] = "HVC or SVC instruction execution",
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[22] = "HVC or SVC instruction execution",
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[23] = "SMC instruction execution in AArch64 state",
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[24] = "MSR, MRS, or System instruction execution in AArch64 state",
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[31] = "IMPLEMENTATION DEFINED exception to EL3",
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[32] = "an Instruction abort",
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[33] = "an Instruction abort",
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[34] = "an Illegal execution state, or a PC or SP alignment fault",
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[36] = "a Data abort, from lower exception level",
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[37] = "a Data abort, from current exception level",
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[38] = "an Illegal execution state, or a PC or SP alignment fault",
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[40] = "a trapped Floating-point exception",
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[44] = "a trapped Floating-point exception",
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[47] = "SError interrupt",
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[48] = "a Breakpoint or Vector Catch debug event",
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[49] = "a Breakpoint or Vector Catch debug event",
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[50] = "a Software Step debug event",
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[51] = "a Software Step debug event",
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[52] = "a Watchpoint debug event",
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[53] = "a Watchpoint debug event",
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[56] = "execution of a Software Breakpoint instructio",
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};
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printf("\n");
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/* PC/LR/SP ... */
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printf("* Reason: Exception from %s\n", esr_bits_ec[REG_BITS(regs->esr, 26, 0x3f)]);
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if (gd->flags & GD_FLG_RELOC) {
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printf("* PC = %016lx\n", regs->elr - gd->reloc_off);
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printf("* LR = %016lx\n", regs->regs[30] - gd->reloc_off);
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} else {
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printf("* ELR(PC) = %016lx\n", regs->elr);
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printf("* LR = %016lx\n", regs->regs[30]);
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}
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printf("* SP = %016lx\n", regs->sp);
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printf("* ESR_EL%d = %016lx\n", el, regs->esr);
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printf("* Reloc Off = %016lx\n\n", gd->reloc_off);
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/* CPU */
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for (i = 0; i < 29; i += 2)
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printf("x%-2d: %016lx x%-2d: %016lx\n",
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i, regs->regs[i], i+1, regs->regs[i+1]);
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printf("\n");
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/* SoC */
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#ifdef CONFIG_ROCKCHIP_CRASH_DUMP
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iomem_show_by_compatible("-cru", 0, 0x400);
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iomem_show_by_compatible("-pmucru", 0, 0x400);
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iomem_show_by_compatible("-grf", 0, 0x400);
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iomem_show_by_compatible("-pmugrf", 0, 0x400);
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#endif
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/* Call trace */
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dump_core_stack(regs);
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}
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#else
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void show_regs(struct pt_regs *regs)
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{
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int i;
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if (gd->flags & GD_FLG_RELOC) {
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printf("ELR: %lx\n", regs->elr - gd->reloc_off);
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printf("LR: %lx\n", regs->regs[30] - gd->reloc_off);
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} else {
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printf("ELR: %lx\n", regs->elr);
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printf("LR: %lx\n", regs->regs[30]);
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}
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printf("ESR: %lx (ec=%ld)\n", regs->esr, REG_BITS(regs->esr, 26, 0x3f));
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for (i = 0; i < 29; i += 2)
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printf("x%-2d: %016lx x%-2d: %016lx\n",
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i, regs->regs[i], i+1, regs->regs[i+1]);
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printf("\n");
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dump_core_stack(regs);
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}
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#endif
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/*
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* do_bad_sync handles the impossible case in the Synchronous Abort vector.
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*/
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void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_irq handles the impossible case in the Irq vector.
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*/
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void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_fiq handles the impossible case in the Fiq vector.
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*/
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void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_error handles the impossible case in the Error vector.
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*/
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void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_sync handles the Synchronous Abort exception.
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*/
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void do_sync(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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#if !CONFIG_IS_ENABLED(IRQ)
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/*
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* do_irq handles the Irq exception.
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*/
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void do_irq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Irq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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#endif
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/*
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* do_fiq handles the Fiq exception.
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*/
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void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Fiq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_error handles the Error exception.
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* Errors are more likely to be processor specific,
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* it is defined with weak attribute and can be redefined
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* in processor specific code.
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*/
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void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Error\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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