/*
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* GIC Initialization Routines.
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*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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/*************************************************************************
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*
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* void gic_init_secure(DistributorBase);
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*
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* Initialize secure copy of GIC at EL3.
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*
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*************************************************************************/
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ENTRY(gic_init_secure)
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/*
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* Initialize Distributor
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* x0: Distributor Base
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*/
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#if defined(CONFIG_GICV3)
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mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */
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/* EnableGrp1S | ARE_S | ARE_NS */
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str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
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ldr w9, [x0, GICD_TYPER]
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and w10, w9, #0x1f /* ITLinesNumber */
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cbz w10, 1f /* No SPIs */
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add x11, x0, (GICD_IGROUPRn + 4)
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add x12, x0, (GICD_IGROUPMODRn + 4)
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mov w9, #~0
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0: str w9, [x11], #0x4
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str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
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sub w10, w10, #0x1
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cbnz w10, 0b
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#elif defined(CONFIG_GICV2)
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mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */
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str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
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ldr w9, [x0, GICD_TYPER]
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and w10, w9, #0x1f /* ITLinesNumber */
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cbz w10, 1f /* No SPIs */
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add x11, x0, GICD_IGROUPRn
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mov w9, #~0 /* Config SPIs as Grp1 */
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str w9, [x11], #0x4
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0: str w9, [x11], #0x4
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sub w10, w10, #0x1
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cbnz w10, 0b
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ldr x1, =GICC_BASE /* GICC_CTLR */
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mov w0, #3 /* EnableGrp0 | EnableGrp1 */
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str w0, [x1]
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mov w0, #1 << 7 /* allow NS access to GICC_PMR */
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str w0, [x1, #4] /* GICC_PMR */
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#endif
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1:
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ret
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ENDPROC(gic_init_secure)
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/*************************************************************************
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* For Gicv2:
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* void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
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* For Gicv3:
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* void gic_init_secure_percpu(ReDistributorBase);
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*
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* Initialize secure copy of GIC at EL3.
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*
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*************************************************************************/
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ENTRY(gic_init_secure_percpu)
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#if defined(CONFIG_GICV3)
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/*
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* Initialize ReDistributor
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* x0: ReDistributor Base
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*/
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mrs x10, mpidr_el1
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lsr x9, x10, #32
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bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
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mov x9, x0
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1: ldr x11, [x9, GICR_TYPER]
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lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
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cmp w10, w11
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b.eq 2f
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add x9, x9, #(2 << 16)
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b 1b
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/* x9: ReDistributor Base Address of Current CPU */
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2: mov w10, #~0x2
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ldr w11, [x9, GICR_WAKER]
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and w11, w11, w10 /* Clear ProcessorSleep */
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str w11, [x9, GICR_WAKER]
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dsb st
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isb
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3: ldr w10, [x9, GICR_WAKER]
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tbnz w10, #2, 3b /* Wait Children be Alive */
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add x10, x9, #(1 << 16) /* SGI_Base */
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mov w11, #~0
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str w11, [x10, GICR_IGROUPRn]
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str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
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mov w11, #0x1 /* Enable SGI 0 */
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str w11, [x10, GICR_ISENABLERn]
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#if CONFIG_IS_ENABLED(IRQ)
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/* Rockchip: check elx */
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switch_el x0, el3_sre, el2_sre, el1_sre
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/* Initialize Cpu Interface */
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el3_sre:
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mrs x10, ICC_SRE_EL3
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orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
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/* Allow EL2 access to ICC_SRE_EL2 */
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msr ICC_SRE_EL3, x10
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isb
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el2_sre:
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mrs x10, ICC_SRE_EL2
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orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
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/* Allow EL1 access to ICC_SRE_EL1 */
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msr ICC_SRE_EL2, x10
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isb
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el1_sre:
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mrs x0, CurrentEL /* check currentEL */
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cmp x0, 0xC
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b.ne el1_ctlr /* currentEL != EL3 */
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el3_ctlr:
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mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
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msr ICC_IGRPEN1_EL3, x10
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isb
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msr ICC_CTLR_EL3, xzr
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isb
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el1_ctlr:
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mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
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msr ICC_IGRPEN1_EL1, x10
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isb
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msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
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isb
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mov x10, #0xf0 /* Non-Secure access to ICC_PMR_EL1 */
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msr ICC_PMR_EL1, x10
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isb
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#else
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/* Initialize Cpu Interface */
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mrs x10, ICC_SRE_EL3
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orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
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/* Allow EL2 access to ICC_SRE_EL2 */
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msr ICC_SRE_EL3, x10
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isb
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mrs x10, ICC_SRE_EL2
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orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
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/* Allow EL1 access to ICC_SRE_EL1 */
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msr ICC_SRE_EL2, x10
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isb
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mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
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msr ICC_IGRPEN1_EL3, x10
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isb
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msr ICC_CTLR_EL3, xzr
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isb
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msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
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isb
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mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
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msr ICC_PMR_EL1, x10
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isb
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#endif
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#elif defined(CONFIG_GICV2)
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/*
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* Initialize SGIs and PPIs
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* x0: Distributor Base
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* x1: Cpu Interface Base
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*/
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mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
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str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
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mov w9, #0x1 /* Enable SGI 0 */
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str w9, [x0, GICD_ISENABLERn]
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/* Initialize Cpu Interface */
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mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
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/* Enable Ack Group1 Interrupt & */
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/* EnableGrp0 & EnableGrp1 */
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str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
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mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
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str w9, [x1, GICC_PMR]
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#endif
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ret
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ENDPROC(gic_init_secure_percpu)
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/*************************************************************************
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* For Gicv2:
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* void gic_kick_secondary_cpus(DistributorBase);
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* For Gicv3:
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* void gic_kick_secondary_cpus(void);
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*
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*************************************************************************/
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ENTRY(gic_kick_secondary_cpus)
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#if defined(CONFIG_GICV3)
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mov x9, #(1 << 40)
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msr ICC_ASGI1R_EL1, x9
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isb
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#elif defined(CONFIG_GICV2)
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mov w9, #0x8000
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movk w9, #0x100, lsl #16
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str w9, [x0, GICD_SGIR]
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#endif
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ret
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ENDPROC(gic_kick_secondary_cpus)
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/*************************************************************************
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* For Gicv2:
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* void gic_wait_for_interrupt(CpuInterfaceBase);
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* For Gicv3:
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* void gic_wait_for_interrupt(void);
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*
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* Wait for SGI 0 from master.
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*
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*************************************************************************/
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ENTRY(gic_wait_for_interrupt)
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#if defined(CONFIG_GICV3)
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gic_wait_for_interrupt_m x9
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#elif defined(CONFIG_GICV2)
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gic_wait_for_interrupt_m x0, w9
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#endif
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ret
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ENDPROC(gic_wait_for_interrupt)
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