/*
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* Enhanced Direct Memory Access (EDMA3) Controller
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _EDMA3_H_
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#define _EDMA3_H_
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#include <linux/stddef.h>
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#define EDMA3_PARSET_NULL_LINK 0xffff
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/*
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* All parameter RAM set options
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* opt field in edma3_param_set_config structure
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*/
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#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
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#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24)
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#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
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#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
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#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21)
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#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
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#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12)
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#define EDMA3_SLOPT_FIFO_WIDTH_8 0
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#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8)
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#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8)
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#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8)
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#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8)
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#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8)
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#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8)
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#define EDMA3_SLOPT_STATIC BIT(3)
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#define EDMA3_SLOPT_AB_SYNC BIT(2)
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#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1)
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#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0)
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enum edma3_address_mode {
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INCR = 0,
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FIFO = 1
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};
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enum edma3_fifo_width {
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W8BIT = 0,
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W16BIT = 1,
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W32BIT = 2,
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W64BIT = 3,
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W128BIT = 4,
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W256BIT = 5
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};
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enum edma3_sync_dimension {
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ASYNC = 0,
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ABSYNC = 1
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};
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/* PaRAM slots are laid out like this */
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struct edma3_slot_layout {
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u32 opt;
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u32 src;
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u32 a_b_cnt;
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u32 dst;
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u32 src_dst_bidx;
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u32 link_bcntrld;
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u32 src_dst_cidx;
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u32 ccnt;
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} __packed;
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/*
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* Use this to assign trigger word number of edma3_slot_layout struct.
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* trigger_word_name - is the exact name from edma3_slot_layout.
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*/
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#define EDMA3_TWORD(trigger_word_name)\
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(offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
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struct edma3_slot_config {
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u32 opt;
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u32 src;
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u32 dst;
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int bcnt;
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int acnt;
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int ccnt;
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int src_bidx;
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int dst_bidx;
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int src_cidx;
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int dst_cidx;
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int bcntrld;
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int link;
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};
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struct edma3_channel_config {
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int slot;
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int chnum;
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int complete_code; /* indicate pending complete interrupt */
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int trigger_slot_word; /* only used for qedma */
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};
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void qedma3_start(u32 base, struct edma3_channel_config *cfg);
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void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
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void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
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int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
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void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
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void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
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void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
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enum edma3_fifo_width width);
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void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
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void edma3_set_dest_addr(u32 base, int slot, u32 dst);
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void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
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enum edma3_fifo_width width);
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void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
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void edma3_set_src_addr(u32 base, int slot, u32 src);
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void edma3_set_transfer_params(u32 base, int slot, int acnt,
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int bcnt, int ccnt, u16 bcnt_rld,
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enum edma3_sync_dimension sync_mode);
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void edma3_transfer(unsigned long edma3_base_addr, unsigned int
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edma_slot_num, void *dst, void *src, size_t len);
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#endif
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