/*
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* Multicore Navigator definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _KEYSTONE_NAV_H_
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#define _KEYSTONE_NAV_H_
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define QM_OK 0
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#define QM_ERR -1
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#define QM_DESC_TYPE_HOST 0
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#define QM_DESC_PSINFO_IN_DESCR 0
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#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
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(QM_DESC_PSINFO_IN_DESCR << 22)
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/* Packet Info */
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#define QM_DESC_PINFO_EPIB 1
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#define QM_DESC_PINFO_RETURN_OWN 1
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#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
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(QM_DESC_PINFO_RETURN_OWN << 15)
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struct qm_cfg_reg {
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u32 revision;
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u32 __pad1;
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u32 divert;
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u32 link_ram_base0;
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u32 link_ram_size0;
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u32 link_ram_base1;
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u32 link_ram_size1;
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u32 link_ram_base2;
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u32 starvation[0];
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};
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struct descr_mem_setup_reg {
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u32 base_addr;
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u32 start_idx;
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u32 desc_reg_size;
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u32 _res0;
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};
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struct qm_reg_queue {
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u32 entry_count;
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u32 byte_count;
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u32 packet_size;
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u32 ptr_size_thresh;
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};
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struct qm_config {
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/* QM module addresses */
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u32 stat_cfg; /* status and config */
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struct qm_reg_queue *queue; /* management region */
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u32 mngr_vbusm; /* management region (VBUSM) */
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u32 i_lram; /* internal linking RAM */
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struct qm_reg_queue *proxy;
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u32 status_ram;
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struct qm_cfg_reg *mngr_cfg;
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/* Queue manager config region */
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u32 intd_cfg; /* QMSS INTD config region */
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struct descr_mem_setup_reg *desc_mem;
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/* descritor memory setup region*/
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u32 region_num;
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u32 pdsp_cmd; /* PDSP1 command interface */
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u32 pdsp_ctl; /* PDSP1 control registers */
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u32 pdsp_iram;
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/* QM configuration parameters */
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u32 qpool_num; /* */
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};
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struct qm_host_desc {
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u32 desc_info;
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u32 tag_info;
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u32 packet_info;
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u32 buff_len;
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u32 buff_ptr;
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u32 next_bdptr;
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u32 orig_buff_len;
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u32 orig_buff_ptr;
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u32 timestamp;
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u32 swinfo[3];
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u32 ps_data[20];
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};
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#define HDESC_NUM 256
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int qm_init(void);
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void qm_close(void);
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void qm_push(struct qm_host_desc *hd, u32 qnum);
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struct qm_host_desc *qm_pop(u32 qnum);
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void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
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void *buff_ptr, u32 buff_len);
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struct qm_host_desc *qm_pop_from_free_pool(void);
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void queue_close(u32 qnum);
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/*
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* DMA API
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*/
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#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
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psloc, sopoff, qmgr, qnum) \
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(((einfo & 1) << 30) | \
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((psinfo & 1) << 29) | \
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((rxerr & 1) << 28) | \
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((desc & 3) << 26) | \
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((psloc & 1) << 25) | \
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((sopoff & 0x1ff) << 16) | \
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((qmgr & 3) << 12) | \
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((qnum & 0xfff) << 0))
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#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
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(((fd0qm & 3) << 28) | \
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((fd0qnum & 0xfff) << 16) | \
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((fd1qm & 3) << 12) | \
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((fd1qnum & 0xfff) << 0))
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#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
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#define CPDMA_CHAN_A_TDOWN (1 << 30)
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#define TDOWN_TIMEOUT_COUNT 100
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struct global_ctl_regs {
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u32 revision;
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u32 perf_control;
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u32 emulation_control;
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u32 priority_control;
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u32 qm_base_addr[4];
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};
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struct tx_chan_regs {
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u32 cfg_a;
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u32 cfg_b;
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u32 res[6];
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};
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struct rx_chan_regs {
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u32 cfg_a;
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u32 res[7];
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};
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struct rx_flow_regs {
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u32 control;
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u32 tags;
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u32 tag_sel;
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u32 fdq_sel[2];
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u32 thresh[3];
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};
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struct pktdma_cfg {
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struct global_ctl_regs *global;
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struct tx_chan_regs *tx_ch;
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u32 tx_ch_num;
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struct rx_chan_regs *rx_ch;
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u32 rx_ch_num;
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u32 *tx_sched;
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struct rx_flow_regs *rx_flows;
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u32 rx_flow_num;
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u32 rx_free_q;
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u32 rx_rcv_q;
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u32 tx_snd_q;
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u32 rx_flow; /* flow that is used for RX */
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};
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extern struct pktdma_cfg netcp_pktdma;
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/*
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* packet dma user allocates memory for rx buffers
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* and describe it in the following structure
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*/
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struct rx_buff_desc {
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u8 *buff_ptr;
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u32 num_buffs;
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u32 buff_len;
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u32 rx_flow;
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};
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int ksnav_close(struct pktdma_cfg *pktdma);
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int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
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int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
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void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
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void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
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#endif /* _KEYSTONE_NAV_H_ */
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