/*
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* include/asm-arm/macro.h
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*
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARM_MACRO_H__
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#define __ASM_ARM_MACRO_H__
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#ifdef CONFIG_ARM64
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#include <asm/system.h>
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#endif
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#ifdef __ASSEMBLY__
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/*
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* These macros provide a convenient way to write 8, 16 and 32 bit data
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* to any address.
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* Registers r4 and r5 are used, any data in these registers are
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* overwritten by the macros.
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* The macros are valid for any ARM architecture, they do not implement
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* any memory barriers so caution is recommended when using these when the
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* caches are enabled or on a multi-core system.
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*/
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.macro write32, addr, data
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ldr r4, =\addr
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ldr r5, =\data
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str r5, [r4]
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.endm
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.macro write16, addr, data
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ldr r4, =\addr
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ldrh r5, =\data
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strh r5, [r4]
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.endm
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.macro write8, addr, data
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ldr r4, =\addr
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ldrb r5, =\data
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strb r5, [r4]
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.endm
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/*
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* This macro generates a loop that can be used for delays in the code.
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* Register r4 is used, any data in this register is overwritten by the
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* macro.
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* The macro is valid for any ARM architeture. The actual time spent in the
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* loop will vary from CPU to CPU though.
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*/
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.macro wait_timer, time
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ldr r4, =\time
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1:
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nop
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subs r4, r4, #1
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bcs 1b
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.endm
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#ifdef CONFIG_ARM64
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/*
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* Register aliases.
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*/
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lr .req x30
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/*
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* Branch according to exception level
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*/
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.macro switch_el, xreg, el3_label, el2_label, el1_label
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mrs \xreg, CurrentEL
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cmp \xreg, 0xc
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b.eq \el3_label
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cmp \xreg, 0x8
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b.eq \el2_label
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cmp \xreg, 0x4
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b.eq \el1_label
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.endm
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/*
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* Branch if current processor is a Cortex-A35 core.
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*/
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.macro branch_if_a35_core, xreg, a35_label
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mrs \xreg, midr_el1
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lsr \xreg, \xreg, #4
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and \xreg, \xreg, #0x00000FFF
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cmp \xreg, #0xD04 /* Cortex-A35 MPCore processor. */
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b.eq \a35_label
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.endm
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/*
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* Branch if current processor is a Cortex-A57 core.
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*/
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.macro branch_if_a57_core, xreg, a57_label
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mrs \xreg, midr_el1
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lsr \xreg, \xreg, #4
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and \xreg, \xreg, #0x00000FFF
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cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
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b.eq \a57_label
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.endm
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/*
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* Branch if current processor is a Cortex-A53 core.
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*/
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.macro branch_if_a53_core, xreg, a53_label
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mrs \xreg, midr_el1
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lsr \xreg, \xreg, #4
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and \xreg, \xreg, #0x00000FFF
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cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
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b.eq \a53_label
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.endm
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/*
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* Branch if current processor is a slave,
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* choose processor with all zero affinity value as the master.
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*/
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.macro branch_if_slave, xreg, slave_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg, mpidr_el1
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tst \xreg, #0xff /* Test Affinity 0 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 1 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 2 */
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b.ne \slave_label
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lsr \xreg, \xreg, #16
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tst \xreg, #0xff /* Test Affinity 3 */
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b.ne \slave_label
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#endif
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.endm
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/*
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* Branch if current processor is a master,
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* choose processor with all zero affinity value as the master.
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*/
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.macro branch_if_master, xreg1, xreg2, master_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg1, mpidr_el1
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lsr \xreg2, \xreg1, #32
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lsl \xreg2, \xreg2, #32
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lsl \xreg1, \xreg1, #40
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lsr \xreg1, \xreg1, #40
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orr \xreg1, \xreg1, \xreg2
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cbz \xreg1, \master_label
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#else
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b \master_label
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#endif
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.endm
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/*
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* Switch from EL3 to EL2 for ARMv8
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* @ep: kernel entry point
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* @flag: The execution state flag for lower exception
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* level, ES_TO_AARCH64 or ES_TO_AARCH32
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* @tmp: temporary register
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*
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* For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
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* For loading 64-bit OS, x0 is physical address to the FDT blob.
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* They will be passed to the guest.
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*/
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.macro armv8_switch_to_el2_m, ep, flag, tmp
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msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
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mov \tmp, #CPTR_EL2_RES1
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msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
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/* Initialize Generic Timers */
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msr cntvoff_el2, xzr
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/* Initialize SCTLR_EL2
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*
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* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
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* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
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* EE,WXN,I,SA,C,A,M to 0
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*/
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ldr \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
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SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
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SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
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SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
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msr sctlr_el2, \tmp
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mov \tmp, sp
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msr sp_el2, \tmp /* Migrate SP */
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mrs \tmp, vbar_el3
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msr vbar_el2, \tmp /* Migrate VBAR */
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/* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
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cmp \flag, #ES_TO_AARCH32
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b.eq 1f
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/*
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* The next lower exception level is AArch64, 64bit EL2 | HCE |
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* RES1 (Bits[5:4]) | Non-secure EL0/EL1.
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* and the SMD depends on requirements.
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*/
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#ifdef CONFIG_ARMV8_PSCI
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ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
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SCR_EL3_RES1 | SCR_EL3_NS_EN)
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#else
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ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
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SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
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SCR_EL3_NS_EN)
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#endif
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msr scr_el3, \tmp
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/* Return to the EL2_SP2 mode from EL3 */
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ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
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msr spsr_el3, \tmp
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msr elr_el3, \ep
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eret
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1:
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/*
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* The next lower exception level is AArch32, 32bit EL2 | HCE |
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* SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
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*/
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ldr \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
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SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
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SCR_EL3_NS_EN)
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msr scr_el3, \tmp
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/* Return to AArch32 Hypervisor mode */
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ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
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SPSR_EL_M_HYP)
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msr spsr_el3, \tmp
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msr elr_el3, \ep
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eret
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.endm
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/*
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* Switch from EL2 to EL1 for ARMv8
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* @ep: kernel entry point
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* @flag: The execution state flag for lower exception
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* level, ES_TO_AARCH64 or ES_TO_AARCH32
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* @tmp: temporary register
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*
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* For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
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* For loading 64-bit OS, x0 is physical address to the FDT blob.
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* They will be passed to the guest.
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*/
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.macro armv8_switch_to_el1_m, ep, flag, tmp
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/* Initialize Generic Timers */
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mrs \tmp, cnthctl_el2
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/* Enable EL1 access to timers */
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orr \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
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CNTHCTL_EL2_EL1PCTEN_EN)
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msr cnthctl_el2, \tmp
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msr cntvoff_el2, xzr
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/* Initilize MPID/MPIDR registers */
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mrs \tmp, midr_el1
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msr vpidr_el2, \tmp
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mrs \tmp, mpidr_el1
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msr vmpidr_el2, \tmp
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/* Disable coprocessor traps */
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mov \tmp, #CPTR_EL2_RES1
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msr cptr_el2, \tmp /* Disable coprocessor traps to EL2 */
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msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
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mov \tmp, #CPACR_EL1_FPEN_EN
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msr cpacr_el1, \tmp /* Enable FP/SIMD at EL1 */
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/* SCTLR_EL1 initialization
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*
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* setting RES1 bits (29,28,23,22,20,11) to 1
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* and RES0 bits (31,30,27,21,17,13,10,6) +
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* UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
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* CP15BEN,SA0,SA,C,A,M to 0
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*/
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ldr \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
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SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
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SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
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SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
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SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
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SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
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SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
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SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
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SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
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msr sctlr_el1, \tmp
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mov \tmp, sp
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msr sp_el1, \tmp /* Migrate SP */
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mrs \tmp, vbar_el2
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msr vbar_el1, \tmp /* Migrate VBAR */
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/* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
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cmp \flag, #ES_TO_AARCH32
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b.eq 1f
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/* Initialize HCR_EL2 */
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ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
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msr hcr_el2, \tmp
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/* Return to the EL1_SP1 mode from EL2 */
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ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
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msr spsr_el2, \tmp
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msr elr_el2, \ep
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eret
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1:
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/* Initialize HCR_EL2 */
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ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
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msr hcr_el2, \tmp
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/* Return to AArch32 Supervisor mode from EL2 */
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ldr \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
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SPSR_EL_M_SVC)
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msr spsr_el2, \tmp
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msr elr_el2, \ep
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eret
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.endm
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#if defined(CONFIG_GICV3)
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.macro gic_wait_for_interrupt_m xreg1
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0 : wfi
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mrs \xreg1, ICC_IAR1_EL1
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msr ICC_EOIR1_EL1, \xreg1
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cbnz \xreg1, 0b
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.endm
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#elif defined(CONFIG_GICV2)
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.macro gic_wait_for_interrupt_m xreg1, wreg2
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0 : wfi
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ldr \wreg2, [\xreg1, GICC_AIAR]
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str \wreg2, [\xreg1, GICC_AEOIR]
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and \wreg2, \wreg2, #0x3ff
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cbnz \wreg2, 0b
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.endm
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#endif
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#endif /* CONFIG_ARM64 */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_MACRO_H__ */
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