/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#define PAYLOAD_ARG_CNT 5
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#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
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enum {
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IDCODE,
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VERSION,
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};
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enum {
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ZYNQMP_SILICON_V1,
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ZYNQMP_SILICON_V2,
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ZYNQMP_SILICON_V3,
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ZYNQMP_SILICON_V4,
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};
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enum {
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TCM_LOCK,
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TCM_SPLIT,
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};
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int zynq_slcr_get_mio_pin_status(const char *periph);
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unsigned int zynqmp_get_silicon_version(void);
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void psu_init(void);
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void handoff_setup(void);
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void zynqmp_pmufw_version(void);
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int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
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int zynqmp_mmio_read(const u32 address, u32 *value);
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int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
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u32 *ret_payload);
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void initialize_tcm(bool mode);
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int chip_id(unsigned char id);
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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