/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
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#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
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#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
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#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
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#define ZYNQ_I2C_BASEADDR0 0xFF020000
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#define ZYNQ_I2C_BASEADDR1 0xFF030000
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#define ARASAN_NAND_BASEADDR 0xFF100000
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#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
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#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
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#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
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#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
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#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
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#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
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#define PS_MODE0 BIT(0)
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#define PS_MODE1 BIT(1)
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#define PS_MODE2 BIT(2)
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#define PS_MODE3 BIT(3)
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struct crlapb_regs {
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u32 reserved0[36];
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u32 cpu_r5_ctrl; /* 0x90 */
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u32 reserved1[37];
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u32 timestamp_ref_ctrl; /* 0x128 */
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u32 reserved2[53];
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u32 boot_mode; /* 0x200 */
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u32 reserved3[14];
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u32 rst_lpd_top; /* 0x23C */
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u32 reserved4[4];
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u32 boot_pin_ctrl; /* 0x250 */
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u32 reserved5[21];
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};
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
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#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
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struct iou_scntr_secure {
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u32 counter_control_register;
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u32 reserved0[7];
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u32 base_frequency_id_register;
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};
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#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
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/* Bootmode setting values */
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#define BOOT_MODES_MASK 0x0000000F
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#define QSPI_MODE_24BIT 0x00000001
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#define QSPI_MODE_32BIT 0x00000002
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#define SD_MODE 0x00000003 /* sd 0 */
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#define SD_MODE1 0x00000005 /* sd 1 */
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#define NAND_MODE 0x00000004
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#define EMMC_MODE 0x00000006
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#define USB_MODE 0x00000007
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#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
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#define JTAG_MODE 0x00000000
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#define BOOT_MODE_USE_ALT 0x100
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#define BOOT_MODE_ALT_SHIFT 12
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/* SW secondary boot modes 0xa - 0xd */
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#define SW_USBHOST_MODE 0x0000000A
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#define SW_SATA_MODE 0x0000000B
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#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
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struct iou_slcr_regs {
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u32 mio_pin[78];
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u32 reserved[442];
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};
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#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
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#define ZYNQMP_RPU_BASEADDR 0xFF9A0000
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struct rpu_regs {
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u32 rpu_glbl_ctrl;
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u32 reserved0[63];
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u32 rpu0_cfg; /* 0x100 */
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u32 reserved1[63];
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u32 rpu1_cfg; /* 0x200 */
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};
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#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
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#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
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struct crfapb_regs {
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u32 reserved0[65];
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u32 rst_fpd_apu; /* 0x104 */
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u32 reserved1;
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};
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#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
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#define ZYNQMP_APU_BASEADDR 0xFD5C0000
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struct apu_regs {
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u32 reserved0[16];
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u32 rvbar_addr0_l; /* 0x40 */
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u32 rvbar_addr0_h; /* 0x44 */
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u32 reserved1[20];
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};
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#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
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/* Board version value */
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#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
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#define ZYNQMP_CSU_VERSION_SILICON 0x0
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#define ZYNQMP_CSU_VERSION_EP108 0x1
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#define ZYNQMP_CSU_VERSION_VELOCE 0x2
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#define ZYNQMP_CSU_VERSION_QEMU 0x3
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#define ZYNQMP_SILICON_VER_MASK 0xF000
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#define ZYNQMP_SILICON_VER_SHIFT 12
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struct csu_regs {
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u32 reserved0[17];
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u32 version;
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};
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#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
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#define ZYNQMP_PMU_BASEADDR 0xFFD80000
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struct pmu_regs {
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u32 reserved[18];
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u32 gen_storage6; /* 0x48 */
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};
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#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
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#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040
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#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044
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#endif /* _ASM_ARCH_HARDWARE_H */
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