/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _TEGRA30_H_
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#define _TEGRA30_H_
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#define NV_PA_MC_BASE 0x7000F000
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#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
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#include <asm/arch-tegra/tegra.h>
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#define TEGRA_USB1_BASE 0x7D000000
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#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
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#define MAX_NUM_CPU 4
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#endif /* TEGRA30_H */
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