/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/* Tegra30 clock control functions */
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#ifndef _TEGRA30_CLOCK_H_
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#define _TEGRA30_CLOCK_H_
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#include <asm/arch-tegra/clock.h>
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
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#define OSC_FREQ_SHIFT 28
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#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
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int tegra_plle_enable(void);
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#endif /* _TEGRA30_CLOCK_H_ */
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