/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA210_TEGRA_H_
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#define _TEGRA210_TEGRA_H_
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#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */
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#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */
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#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
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#define NV_PA_SDRAM_BASE 0x80000000
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#include <asm/arch-tegra/tegra.h>
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#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */
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#undef NVBOOTINFOTABLE_BCTSIZE
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#undef NVBOOTINFOTABLE_BCTPTR
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#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
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#define MAX_NUM_CPU 4
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#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
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#define TEGRA_USB1_BASE 0x7D000000
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#endif /* _TEGRA210_TEGRA_H_ */
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