/*
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* (C) Copyright 2010-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra210 clock control definitions */
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#ifndef _TEGRA210_CLOCK_H_
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#define _TEGRA210_CLOCK_H_
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#include <asm/arch-tegra/clock.h>
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
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#define OSC_FREQ_SHIFT 28
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#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
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/* PLL bits that differ from generic clk_rst.h */
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#define PLLC_RESET 30
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#define PLLC_IDDQ 27
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#define PLLD_ENABLE_CLK 21
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#define PLLD_EN_LCKDET 28
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int tegra_plle_enable(void);
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#endif /* _TEGRA210_CLOCK_H_ */
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