/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA124_FLOW_H_
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#define _TEGRA124_FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events; /* offset 0x00 */
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u32 halt_cop_events; /* offset 0x04 */
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u32 cpu_csr; /* offset 0x08 */
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u32 cop_csr; /* offset 0x0c */
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u32 xrq_events; /* offset 0x10 */
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u32 halt_cpu1_events; /* offset 0x14 */
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u32 cpu1_csr; /* offset 0x18 */
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u32 halt_cpu2_events; /* offset 0x1c */
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u32 cpu2_csr; /* offset 0x20 */
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u32 halt_cpu3_events; /* offset 0x24 */
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u32 cpu3_csr; /* offset 0x28 */
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u32 cluster_control; /* offset 0x2c */
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u32 halt_cop1_events; /* offset 0x30 */
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u32 halt_cop1_csr; /* offset 0x34 */
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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u32 flow_dbg_sel; /* offset 0x44 */
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u32 flow_dbg_cnt0; /* offset 0x48 */
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u32 flow_dbg_cnt1; /* offset 0x4c */
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u32 flow_dbg_qual; /* offset 0x50 */
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u32 flow_ctlr_spare; /* offset 0x54 */
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u32 ram_repair_cluster1;/* offset 0x58 */
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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#define EVENT_MSEC (1 << 24)
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#define EVENT_USEC (1 << 25)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
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#define ACTIVE_LP (1 << 0)
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/* CPUn_CSR_0 */
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#define CSR_ENABLE (1 << 0)
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#define CSR_IMMEDIATE_WAKE (1 << 3)
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#define CSR_WAIT_WFI_SHIFT 8
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#define CSR_PWR_OFF_STS (1 << 16)
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/* RAM_REPAIR, 0x40, 0x58 */
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enum {
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RAM_REPAIR_REQ = 0x1 << 0,
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RAM_REPAIR_STS = 0x1 << 1,
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};
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#endif /* _TEGRA124_FLOW_H_ */
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