/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _TEGRA114_H_
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#define _TEGRA114_H_
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#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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#define NV_PA_MC_BASE 0x70019000
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#include <asm/arch-tegra/tegra.h>
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#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
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#undef NVBOOTINFOTABLE_BCTSIZE
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#undef NVBOOTINFOTABLE_BCTPTR
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#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
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#define MAX_NUM_CPU 4
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#endif /* TEGRA114_H */
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