/*
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* (C) Copyright 2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA114_MC_H_
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#define _TEGRA114_MC_H_
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/**
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* Defines the memory controller registers we need/care about
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*/
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struct mc_ctlr {
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u32 reserved0[4]; /* offset 0x00 - 0x0C */
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u32 mc_smmu_config; /* offset 0x10 */
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u32 mc_smmu_tlb_config; /* offset 0x14 */
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u32 mc_smmu_ptc_config; /* offset 0x18 */
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u32 mc_smmu_ptb_asid; /* offset 0x1C */
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u32 mc_smmu_ptb_data; /* offset 0x20 */
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u32 reserved1[3]; /* offset 0x24 - 0x2C */
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u32 mc_smmu_tlb_flush; /* offset 0x30 */
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u32 mc_smmu_ptc_flush; /* offset 0x34 */
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u32 reserved2[6]; /* offset 0x38 - 0x4C */
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u32 mc_emem_cfg; /* offset 0x50 */
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u32 mc_emem_adr_cfg; /* offset 0x54 */
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u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
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u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
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u32 reserved3[12]; /* offset 0x60 - 0x8C */
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u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
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u32 reserved4[338]; /* offset 0x100 - 0x644 */
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u32 mc_video_protect_bom; /* offset 0x648 */
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u32 mc_video_protect_size_mb; /* offset 0x64c */
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u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
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};
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#endif /* _TEGRA114_MC_H_ */
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