/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SCU_H_
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#define _SCU_H_
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/* ARM Snoop Control Unit (SCU) registers */
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struct scu_ctlr {
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uint scu_ctrl; /* SCU Control Register, offset 00 */
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uint scu_cfg; /* SCU Config Register, offset 04 */
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uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
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uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
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uint scu_reserved0[12]; /* reserved, offset 10-3C */
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uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
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uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
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uint scu_reserved1[2]; /* reserved, offset 48-4C */
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uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
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uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
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};
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#define SCU_CTRL_ENABLE (1 << 0)
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#endif /* SCU_H */
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