/*
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* (C) Copyright 2010-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_GP_PADCTRL_H_
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#define _TEGRA_GP_PADCTRL_H_
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#define GP_HIDREV 0x804
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/* bit fields definitions for APB_MISC_GP_HIDREV register */
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#define HIDREV_CHIPID_SHIFT 8
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#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
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#define HIDREV_MAJORPREV_SHIFT 4
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#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
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/* CHIPID field returned from APB_MISC_GP_HIDREV register */
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#define CHIPID_TEGRA20 0x20
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#define CHIPID_TEGRA30 0x30
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#define CHIPID_TEGRA114 0x35
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#define CHIPID_TEGRA124 0x40
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#define CHIPID_TEGRA210 0x21
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#endif /* _TEGRA_GP_PADCTRL_H_ */
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