/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FUSE_H_
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#define _FUSE_H_
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/* FUSE registers */
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struct fuse_regs {
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u32 reserved0[64]; /* 0x00 - 0xFC: */
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u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
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u32 reserved1[3]; /* 0x104 - 0x10c: */
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u32 sku_info; /* 0x110 */
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u32 reserved2[13]; /* 0x114 - 0x144: */
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u32 fa; /* 0x148: FUSE_FA */
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u32 reserved3[21]; /* 0x14C - 0x19C: */
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u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
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};
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#endif /* ifndef _FUSE_H_ */
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