/*
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* (C) Copyright 2010-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/types.h>
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/* Stabilization delays, in usec */
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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#define SUPER_CCLK_DIVIDER 0x80000000
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/* Calculate clock fractional divider value from ref and target frequencies */
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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/* Calculate clock frequency value from reference and clock divider value */
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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/* AVP/CPU ID */
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
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#define PG_UP_TAG_0 0x0
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/* AP base physical address of internal SRAM */
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#define NV_PA_BASE_SRAM 0x40000000
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
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#define FLOW_MODE_STOP 2
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#define HALT_COP_EVENT_JTAG (1 << 28)
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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/* This is the main entry into U-Boot, used by the Cortex-A9 */
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extern void _start(void);
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/**
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* Works out the SOC/SKU type used for clocks settings
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*
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* @return SOC type - see TEGRA_SOC...
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*/
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int tegra_get_chip_sku(void);
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/**
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* Returns the pure SOC (chip ID) from the HIDREV register
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*
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* @return SOC ID - see CHIPID_TEGRAxx...
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*/
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int tegra_get_chip(void);
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/**
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* Returns the SKU ID from the sku_info register
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*
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* @return SKU ID - see SKU_ID_Txx...
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*/
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int tegra_get_sku_info(void);
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/* Do any chip-specific cache config */
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void config_cache(void);
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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bool tegra_cpu_is_non_secure(void);
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#endif
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