/*
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* (C) Copyright 2011
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* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MACH_STM32_H_
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#define _MACH_STM32_H_
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#include <asm/arch-stm32/stm32f.h>
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/*
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* Peripheral memory map
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*/
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#define STM32_SYSMEM_BASE 0x1FFF0000
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#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
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#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
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#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
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#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
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#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
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#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
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#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
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#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
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#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
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/*
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* Register maps
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*/
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struct stm32_u_id_regs {
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u32 u_id_low;
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u32 u_id_mid;
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u32 u_id_high;
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};
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struct stm32_rcc_regs {
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u32 cr; /* RCC clock control */
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u32 pllcfgr; /* RCC PLL configuration */
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u32 cfgr; /* RCC clock configuration */
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u32 cir; /* RCC clock interrupt */
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u32 ahb1rstr; /* RCC AHB1 peripheral reset */
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u32 ahb2rstr; /* RCC AHB2 peripheral reset */
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u32 ahb3rstr; /* RCC AHB3 peripheral reset */
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u32 rsv0;
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u32 apb1rstr; /* RCC APB1 peripheral reset */
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u32 apb2rstr; /* RCC APB2 peripheral reset */
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u32 rsv1[2];
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u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
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u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
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u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
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u32 rsv2;
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u32 apb1enr; /* RCC APB1 peripheral clock enable */
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u32 apb2enr; /* RCC APB2 peripheral clock enable */
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u32 rsv3[2];
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u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
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u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
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u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
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u32 rsv4;
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u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
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u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
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u32 rsv5[2];
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u32 bdcr; /* RCC Backup domain control */
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u32 csr; /* RCC clock control & status */
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u32 rsv6[2];
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u32 sscgr; /* RCC spread spectrum clock generation */
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u32 plli2scfgr; /* RCC PLLI2S configuration */
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u32 pllsaicfgr;
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u32 dckcfgr;
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};
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struct stm32_pwr_regs {
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u32 cr;
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u32 csr;
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};
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/*
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* Registers access macros
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*/
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#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
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#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
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static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 16 * 1024,
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[4] = 64 * 1024,
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[5 ... 11] = 128 * 1024
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};
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#endif /* _MACH_STM31_H_ */
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