/*
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* (C) Copyright 2015, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
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#define __ARCH_ARM_MACH_S32V234_MMDC_H__
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#define MMDC0 0
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#define MMDC1 1
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#define MMDC_MDCTL 0x0
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#define MMDC_MDPDC 0x4
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#define MMDC_MDOTC 0x8
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#define MMDC_MDCFG0 0xC
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#define MMDC_MDCFG1 0x10
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#define MMDC_MDCFG2 0x14
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#define MMDC_MDMISC 0x18
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#define MMDC_MDSCR 0x1C
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#define MMDC_MDREF 0x20
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#define MMDC_MDRWD 0x2C
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#define MMDC_MDOR 0x30
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#define MMDC_MDMRR 0x34
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#define MMDC_MDCFG3LP 0x38
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#define MMDC_MDMR4 0x3C
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#define MMDC_MDASP 0x40
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#define MMDC_MAARCR 0x400
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#define MMDC_MAPSR 0x404
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#define MMDC_MAEXIDR0 0x408
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#define MMDC_MAEXIDR1 0x40C
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#define MMDC_MADPCR0 0x410
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#define MMDC_MADPCR1 0x414
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#define MMDC_MADPSR0 0x418
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#define MMDC_MADPSR1 0x41C
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#define MMDC_MADPSR2 0x420
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#define MMDC_MADPSR3 0x424
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#define MMDC_MADPSR4 0x428
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#define MMDC_MADPSR5 0x42C
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#define MMDC_MASBS0 0x430
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#define MMDC_MASBS1 0x434
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#define MMDC_MAGENP 0x440
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#define MMDC_MPZQHWCTRL 0x800
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#define MMDC_MPWLGCR 0x808
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#define MMDC_MPWLDECTRL0 0x80C
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#define MMDC_MPWLDECTRL1 0x810
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#define MMDC_MPWLDLST 0x814
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#define MMDC_MPODTCTRL 0x818
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#define MMDC_MPRDDQBY0DL 0x81C
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#define MMDC_MPRDDQBY1DL 0x820
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#define MMDC_MPRDDQBY2DL 0x824
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#define MMDC_MPRDDQBY3DL 0x828
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#define MMDC_MPDGCTRL0 0x83C
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#define MMDC_MPDGCTRL1 0x840
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#define MMDC_MPDGDLST0 0x844
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#define MMDC_MPRDDLCTL 0x848
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#define MMDC_MPRDDLST 0x84C
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#define MMDC_MPWRDLCTL 0x850
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#define MMDC_MPWRDLST 0x854
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#define MMDC_MPZQLP2CTL 0x85C
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#define MMDC_MPRDDLHWCTL 0x860
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#define MMDC_MPWRDLHWCTL 0x864
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#define MMDC_MPRDDLHWST0 0x868
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#define MMDC_MPRDDLHWST1 0x86C
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#define MMDC_MPWRDLHWST1 0x870
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#define MMDC_MPWRDLHWST2 0x874
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#define MMDC_MPWLHWERR 0x878
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#define MMDC_MPDGHWST0 0x87C
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#define MMDC_MPDGHWST1 0x880
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#define MMDC_MPDGHWST2 0x884
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#define MMDC_MPDGHWST3 0x888
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#define MMDC_MPPDCMPR1 0x88C
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#define MMDC_MPPDCMPR2 0x890
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#define MMDC_MPSWDAR0 0x894
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#define MMDC_MPSWDRDR0 0x898
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#define MMDC_MPSWDRDR1 0x89C
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#define MMDC_MPSWDRDR2 0x8A0
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#define MMDC_MPSWDRDR3 0x8A4
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#define MMDC_MPSWDRDR4 0x8A8
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#define MMDC_MPSWDRDR5 0x8AC
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#define MMDC_MPSWDRDR6 0x8B0
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#define MMDC_MPSWDRDR7 0x8B4
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#define MMDC_MPMUR0 0x8B8
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#define MMDC_MPDCCR 0x8C0
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#define MMDC_MPMUR0_FRC_MSR (1 << 11)
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#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)
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#endif
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