/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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* Author: Zhihuan He <huan.he@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H
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#define _ASM_ARCH_SDRAM_RV1108_PCTL_PHY_H
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#include <common.h>
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struct ddr_pctl {
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u32 scfg;
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[(0x40 - 0x10) / 4];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 cmdtstaten;
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u32 reserved1[(0x60 - 0x54) / 4];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[(0x7c - 0x6c) / 4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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u32 mstat;
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u32 lpddr2zqcfg;
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u32 reserved3;
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u32 dtupdes;
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u32 dtuna;
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u32 dtune;
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u32 dtuprd0;
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u32 dtuprd1;
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[(0xc0 - 0xb4) / 4];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 trefi_mem_ddr3;
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u32 reserved5[(0x180 - 0x14c) / 4];
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u32 ecccfg;
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u32 ecctst;
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u32 eccclr;
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u32 ecclog;
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u32 reserved6[(0x200 - 0x190) / 4];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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u32 dtuectl;
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u32 dtuwd0;
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u32 dtuwd1;
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u32 dtuwd2;
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u32 dtuwd3;
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u32 dtuwdm;
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u32 dturd0;
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u32 dturd1;
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u32 dturd2;
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u32 dturd3;
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u32 dtulfsrwd;
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u32 dtulfsrrd;
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u32 dtueaf;
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u32 dfitctrldelay;
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u32 dfiodtcfg;
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u32 dfiodtcfg1;
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u32 dfiodtrankmap;
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u32 dfitphywrdata;
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u32 dfitphywrlat;
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u32 dfitphywrdatalat;
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u32 reserved7;
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[(0x270 - 0x268) / 4];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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u32 dfitphyupdtype3;
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u32 dfitctrlupdmin;
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u32 dfitctrlupdmax;
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u32 dfitctrlupddly;
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u32 reserved9;
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[(0x2ac - 0x29c) / 4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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u32 dfitrrdlvlen;
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u32 dfitrrdlvlgateen;
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u32 dfiststat0;
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u32 dfistcfg0;
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u32 dfistcfg1;
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u32 reserved11;
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u32 dfitdramclken;
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u32 dfitdramclkdis;
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[(0x2f0 - 0x2e4) / 4];
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u32 dfilpcfg0;
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u32 reserved13[(0x300 - 0x2f4) / 4];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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u32 dfitrrdlvlresp0;
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u32 dfitrrdlvlresp1;
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u32 dfitrrdlvlresp2;
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u32 dfitrwrlvldelay0;
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u32 dfitrwrlvldelay1;
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u32 dfitrwrlvldelay2;
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u32 dfitrrdlvldelay0;
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u32 dfitrrdlvldelay1;
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u32 dfitrrdlvldelay2;
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u32 dfitrrdlvlgatedelay0;
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[(0x3f8 - 0x340) / 4];
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u32 ipvr;
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u32 iptr;
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};
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check_member(ddr_pctl, iptr, 0x03fc);
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struct ddr_phy {
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u32 phy_reg0;
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u32 phy_reg1;
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u32 phy_reg2;
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u32 phy_reg3;
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u32 reserved0;
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u32 phy_reg5;
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u32 phy_reg6;
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u32 reserveds1[(0x24 - 0x1c) / 4];
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u32 phy_reg9;
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u32 reserveds2[(0x2c - 0x28) / 4];
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u32 phy_regb;
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u32 phy_regc;
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u32 reserveds3[(0x44 - 0x34) / 4];
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u32 phy_reg11;
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u32 phy_reg12;
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u32 phy_reg13;
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u32 phy_reg14;
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u32 reserved4;
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u32 phy_reg16;
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u32 phy_reg17;
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u32 phy_reg18;
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u32 reserveds5[(0x80 - 0x64) / 4];
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u32 phy_reg20;
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u32 phy_reg21;
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u32 reserveds6[(0x98 - 0x88) / 4];
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u32 phy_reg26;
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u32 phy_reg27;
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u32 phy_reg28;
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u32 reserveds7[(0xac - 0xa4) / 4];
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u32 phy_reg2b;
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u32 phy_reg2c;
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u32 reserveds8[(0xb8 - 0xb4) / 4];
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u32 phy_reg2e;
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u32 phy_reg2f;
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u32 phy_reg30;
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u32 phy_reg31;
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u32 reserveds9[(0xd8 - 0xc8) / 4];
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u32 phy_reg36;
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u32 phy_reg37;
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u32 phy_reg38;
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u32 reserveds10[(0xec - 0xe4) / 4];
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u32 phy_reg3b;
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u32 phy_reg3c;
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u32 reserveds11[(0xf8 - 0xf4) / 4];
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u32 phy_reg3e;
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u32 phy_reg3f;
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u32 reserveds12[(0x1c0 - 0x100) / 4];
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u32 phy_reg_skew_cs0data[(0x218 - 0x1c0) / 4];
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u32 reserveds13[(0x28c - 0x218) / 4];
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u32 phy_vref;
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/*dll bypass switch reg,0x290*/
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u32 phy_regdll;
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u32 reserveds14[(0x2c0 - 0x294) / 4];
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u32 phy_reg_ca_skew[(0x2f8 - 0x2c0) / 4];
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u32 reserveds15[(0x300 - 0x2f8) / 4];
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u32 phy_reg_skew_cs1data[(0x358 - 0x300) / 4];
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u32 reserveds16[(0x3c0 - 0x358) / 4];
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u32 phy_regf0;
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u32 phy_regf1;
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u32 reserveds17[(0x3e4 - 0x3c8) / 4];
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u32 phy_regf9;
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u32 phy_regfa;
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u32 phy_regfb;
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u32 phy_regfc;
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u32 reserved18;
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u32 reserved19;
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u32 phy_regff;
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};
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check_member(ddr_phy, phy_regff, 0x03fc);
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union noc_timing_t {
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u32 d32;
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struct {
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unsigned acttoact : 6;
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unsigned rdtomiss : 6;
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unsigned wrtomiss : 6;
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unsigned burstlen : 3;
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unsigned rdtowr : 5;
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unsigned wrtord : 5;
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unsigned bwratio : 1;
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} b;
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};
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union noc_activate_t {
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u32 d32;
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struct {
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unsigned rrd : 4;
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unsigned faw : 6;
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unsigned fawbank : 1;
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unsigned reserved : 21;
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} b;
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};
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struct ddr_timing {
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u32 freq;
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struct pctl_timing {
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 trefi_mem_ddr3;
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} pctl_timing;
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struct phy_timing {
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u32 mr[4];
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u32 bl;
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u32 cl_al;
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} phy_timing;
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union noc_timing_t noc_timing;
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u32 readlatency;
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union noc_activate_t activate;
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u32 devtodev;
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};
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struct ddr_config {
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/*
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* 000: lpddr
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* 001: ddr
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* 010: ddr2
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* 011: ddr3
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* 100: lpddr2-s2
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* 101: lpddr2-s4
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* 110: lpddr3
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*/
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u32 ddr_type;
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u32 chn_cnt;
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u32 rank;
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u32 cs0_row;
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u32 cs1_row;
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/* 2: 4bank, 3: 8bank */
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u32 bank;
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u32 col;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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u32 dbw;
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/* bw(0: 8bit, 1: 16bit, 2: 32bit) */
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u32 bw;
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};
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struct ddr_schedule {
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u32 col;
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u32 bank;
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u32 row;
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};
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enum {
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PHY_LOW_SPEED_MHZ = 400,
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/* PHY_REG0 */
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CHN_ENABLE_SHIFT = 4,
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DQ_16BIT_EN_MASK = 3 << 4,
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DQ_16BIT_EN = 3 << 4,
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DQ_32BIT_EN_MASK = 0xf << 4,
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DQ_32BIT_EN = 0xf << 4,
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RESET_DIGITAL_CORE_SHIFT = 3,
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RESET_DIGITAL_CORE_MASK = 1 << RESET_DIGITAL_CORE_SHIFT,
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RESET_DIGITAL_CORE_ACT = 0,
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RESET_DIGITAL_CORE_DIS = 1,
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RESET_ANALOG_LOGIC_SHIFT = 2,
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RESET_ANALOG_LOGIC_MASK = 1 << RESET_ANALOG_LOGIC_SHIFT,
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RESET_ANALOG_LOGIC_ACT = 0,
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RESET_ANALOG_LOGIC_DIS = 1,
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/* PHY_REG1 */
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MEMORY_SELECT_DDR3 = 0,
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MEMORY_SELECT_DDR2 = 1,
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MEMORY_SELECT_LPDDR2 = 2,
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PHY_BL_8 = 1 << 2,
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PHY_BL_4 = 0 << 2,
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/* PHY_REG2 */
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DQS_GATE_TRAINING_SEL_CS0 = 1 << 5,
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DQS_GATE_TRAINING_ACT = 1,
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DQS_GATE_TRAINING_DIS = 0,
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/* PHY_REG12 */
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CMD_PRCOMP_SHIFT = 3,
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CMD_PRCOMP_MASK = 0x1f << CMD_PRCOMP_SHIFT,
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/* DDRPHY_REG13 */
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CMD_DLL_BYPASS_SHIFT = 4,
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CMD_DLL_BYPASS = 1,
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CMD_DLL_BYPASS_MASK = 1,
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CMD_DLL_BYPASS_DISABLE = 0,
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/* DDRPHY_REG14 */
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CK_DLL_BYPASS_SHIFT = 3,
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CK_DLL_BYPASS = 1,
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CK_DLL_BYPASS_DISABLE = 0,
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/* DDRPHY_REG26 */
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LEFT_CHN_A_DQ_DLL_SHIFT = 4,
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LEFT_CHN_A_DQ_DLL_BYPASS = 1,
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LEFT_CHN_A_DQ_DLL_BYPASS_MASK = 1,
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LEFT_CHN_A_DQ_DLL_BYPASS_DIS = 0,
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/* DDRPHY_REG27 */
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LEFT_CHN_A_DQS_DLL_SHIFT = 3,
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LEFT_CHN_A_DQS_DLL_BYPASS = 1,
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LEFT_CHN_A_DQS_DLL_BYPASS_DIS = 0,
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/* DDRPHY_REG28 */
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LEFT_CHN_A_READ_DQS_22_5_DELAY = 1,
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LEFT_CHN_A_READ_DQS_45_DELAY = 2,
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/* DDRPHY_REG36 */
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RIGHT_CHN_A_DQ_DLL_SHIFT = 4,
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RIGHT_CHN_A_DQ_DLL_BYPASS = 1,
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RIGHT_CHN_A_DQ_DLL_BYPASS_MASK = 1,
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RIGHT_CHN_A_DQ_DLL_BYPASS_DIS = 0,
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/* DDRPHY_REG37 */
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RIGHT_CHN_A_DQS_DLL_SHIFT = 3,
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RIGHT_CHN_A_DQS_DLL_BYPASS = 1,
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RIGHT_CHN_A_DQS_DLL_BYPASS_DIS = 0,
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/* DDRPHY_REG38 */
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RIGHT_CHN_A_READ_DQS_22_5_DELAY = 1,
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RIGHT_CHN_A_READ_DQS_45_DELAY = 2,
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/* PHY_REGDLL */
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RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT = 2,
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RIGHT_CHN_A_TX_DQ_BYPASS_SET = 1,
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RIGHT_CHN_A_TX_DQ_BYPASS_DIS = 0,
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LEFT_CHN_A_TX_DQ_BYPASS_SHIFT = 1,
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LEFT_CHN_A_TX_DQ_BYPASS_SET = 1,
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LEFT_CHN_A_TX_DQ_BYPASS_DIS = 0,
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CMD_CK_DLL_BYPASS_SHIFT = 0,
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CMD_CK_DLL_BYPASS_SET = 1,
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CMD_CK_DLL_BYPASS_DIS = 0,
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/* PHY_REGFF */
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CHN_A_TRAINING_DONE_MASK = 3,
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CHN_A_HIGH_8BIT_TRAINING_DONE = 1 << 1,
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CHN_A_LOW_8BIT_TRAINING_DONE = 1,
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};
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/*PCTL*/
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enum {
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/* PCTL_SCTL */
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INIT_STATE = 0,
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CFG_STATE = 1,
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GO_STATE = 2,
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SLEEP_STATE = 3,
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WAKEUP_STATE = 4,
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/* PCTL_STAT*/
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PCTL_CTL_STAT_MASK = 0x7,
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INIT_MEM = 0,
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CONFIG = 1,
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CONFIG_REQ = 2,
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ACCESS = 3,
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ACCESS_REQ = 4,
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LOW_POWER = 5,
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LOW_POWER_ENTRY_REQ = 6,
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LOW_POWER_EXIT_REQ = 7,
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/* PCTL_MCMD */
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START_CMD = 0x80000000,
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RANK_SEL_SHIFT = 20,
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RANK_SEL_CS0 = 1,
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RANK_SEL_CS1 = 2,
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RANK_SEL_CS0_CS1 = 3,
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BANK_ADDR_SHIFT = 17,
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BANK_ADDR_MASK = 0x7,
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CMD_ADDR_SHIFT = 4,
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CMD_ADDR_MASK = 0x1fff,
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LPDDR23_MA_SHIFT = 4,
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LPDDR23_MA_MASK = 0xff,
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LPDDR23_OP_SHIFT = 12,
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LPDDR23_OP_MASK = 0xff,
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DDR3_DLL_RESET = 1 << 8,
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DESELECT_CMD = 0x0,
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PREA_CMD = 0x1,
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REF_CMD = 0x2,
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MRS_CMD = 0x3,
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ZQCS_CMD = 0x4,
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ZQCL_CMD = 0x5,
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RSTL_CMD = 0x6,
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MPR_CMD = 0x8,
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DFICTRLUPD_CMD = 0xa,
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MR0 = 0x0,
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MR1 = 0x1,
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MR2 = 0x2,
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MR3 = 0x3,
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/* PCTL_POWCTL */
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POWER_UP_START = 1,
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POWER_UP_START_MASK = 1,
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/* PCTL_POWSTAT */
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POWER_UP_DONE = 1,
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/*PCTL_PPCFG*/
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PPMEM_EN_MASK = 1,
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PPMEM_EN = 1,
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PPMEM_DIS = 0,
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/* PCTL_TREFI */
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UPD_REF = 0x80000000,
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/* PCTL_DFISTCFG0 */
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DFI_DATA_BYTE_DISABLE_EN_SHIFT = 2,
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DFI_DATA_BYTE_DISABLE_EN = 1,
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DFI_FREQ_RATIO_EN_SHIFT = 1,
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DFI_FREQ_RATIO_EN = 1,
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DFI_INIT_START_SHIFT = 0,
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DFI_INIT_START_EN = 1,
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/* PCTL_DFISTCFG1 */
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DFI_DRAM_CLK_DISABLE_EN_DPD_SHIFT = 1,
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DFI_DRAM_CLK_DISABLE_EN_DPD = 1,
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DFI_DRAM_CLK_DISABLE_EN_SHIFT = 0,
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DFI_DRAM_CLK_DISABLE_EN = 1,
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/* PCTL_DFISTCFG2 */
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PARITY_EN_SHIFT = 1,
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PARITY_EN = 1,
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PARITY_INTR_EN_SHIFT = 0,
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PARITY_INTR_EN = 1,
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/* PCTL_DFILPCFG0 */
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DFI_LP_EN_PD = 1,
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DFI_LP_WAKEUP_PD_SHIFT = 4,
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DFI_LP_WAKEUP_PD_32_CYCLES = 1,
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DFI_LP_EN_SR_SHIFT = 8,
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DFI_LP_EN_SR = 1,
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DFI_LP_WAKEUP_SR_SHIFT = 12,
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DFI_LP_WAKEUP_SR_32_CYCLES = 1,
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DFI_TLP_RESP_SHIFT = 16,
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DFI_TLP_RESP = 5,
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/* PCTL_DFITPHYUPDTYPE0 */
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TPHYUPD_TYPE0 = 1,
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/* PCTL_DFITPHYRDLAT */
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TPHY_RDLAT = 0xd,
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/* PCTL_DFITPHYWRDATA */
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TPHY_WRDATA = 0x0,
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/* PCTL_DFIUPDCFG */
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DFI_PHYUPD_DISABLE = 0 << 1,
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DFI_CTRLUPD_DISABLE = 0,
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/* PCTL_DFIODTCFG */
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RANK0_ODT_WRITE_SEL_SHIFT = 3,
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RANK0_ODT_WRITE_SEL = 1,
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RANK0_ODT_WRITE_DIS = 0,
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RANK1_ODT_WRITE_SEL_SHIFT = 11,
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RANK1_ODT_WRITE_SEL = 1,
|
RANK1_ODT_WRITE_DIS = 0,
|
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/* PCTL_DFIODTCFG1 */
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ODT_LEN_BL8_W_SHIFT = 16,
|
ODT_LEN_BL8_W = 7,
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ODT_LEN_BL8_W_0 = 0,
|
|
/* PCTL_MCFG */
|
MDDR_LPDDR23_CLOCK_STOP_IDLE_DIS = 0 << 24,
|
LPDDR2_EN = 3 << 22,
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DDR3_EN = 1 << 5,
|
DDR2_EN = 0 << 5,
|
LPDDR2_S4 = 1 << 6,
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MEM_BL_8 = 1,
|
MEM_BL_4 = 0,
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MDDR_LPDDR2_BL_4 = 1 << 20,
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MDDR_LPDDR2_BL_8 = 2 << 20,
|
TFAW_CFG_5_TDDR = 1 << 18,
|
TFAW_CFG_6_TDDR = 2 << 18,
|
PD_EXIT_SLOW_EXIT_MODE = 0 << 17,
|
PD_EXIT_FAST_EXIT_MODE = 1 << 17,
|
PD_TYPE_ACT_PD = 1 << 16,
|
PD_IDLE_DISABLE = 0 << 8,
|
PD_IDLE_MASK = 0xff << 8,
|
PD_IDLE_SHIFT = 8,
|
TWO_T_SHIFT = 3,
|
|
/* PCTL_MCFG1 */
|
SR_IDLE_MASK = 0xff,
|
HW_EXIT_IDLE_EN_SHIFT = 31,
|
HW_EXIT_IDLE_EN_MASK = 1 << HW_EXIT_IDLE_EN_SHIFT,
|
HW_EXIT_IDLE_EN = 1 << HW_EXIT_IDLE_EN_SHIFT,
|
|
/* PCTL_SCFG */
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HW_LOW_POWER_EN = 1,
|
};
|
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enum {
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/* PHY_DDR3_RON_RTT */
|
PHY_RON_RTT_DISABLE = 0,
|
PHY_RON_RTT_451OHM = 1,
|
PHY_RON_RTT_225OHM = 2,
|
PHY_RON_RTT_150OHM = 3,
|
PHY_RON_RTT_112OHM = 4,
|
PHY_RON_RTT_90OHM = 5,
|
PHY_RON_RTT_75OHM = 6,
|
PHY_RON_RTT_64OHM = 7,
|
|
PHY_RON_RTT_56OHM = 16,
|
PHY_RON_RTT_50OHM = 17,
|
PHY_RON_RTT_45OHM = 18,
|
PHY_RON_RTT_41OHM = 19,
|
PHY_RON_RTT_37OHM = 20,
|
PHY_RON_RTT_34OHM = 21,
|
PHY_RON_RTT_33OHM = 22,
|
PHY_RON_RTT_30OHM = 23,
|
|
PHY_RON_RTT_28OHM = 24,
|
PHY_RON_RTT_26OHM = 25,
|
PHY_RON_RTT_25OHM = 26,
|
PHY_RON_RTT_23OHM = 27,
|
PHY_RON_RTT_22OHM = 28,
|
PHY_RON_RTT_21OHM = 29,
|
PHY_RON_RTT_20OHM = 30,
|
PHY_RON_RTT_19OHM = 31,
|
};
|
|
#endif
|
