/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_SDRAM_RK3568_H
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#define _ASM_ARCH_SDRAM_RK3568_H
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#include <asm/arch-rockchip/sdram.h>
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#include <asm/arch-rockchip/sdram_common.h>
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/* store result of read and write training, for ddr_dq_eye tool in u-boot */
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#define RW_TRN_RESULT_ADDR (0x2000000 + 0x8000) /* 32M + 32k */
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#define PRINT_STEP 2
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#undef FSP_NUM
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#undef CS_NUM
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#undef BYTE_NUM
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#define FSP_NUM 4
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#define CS_NUM 4
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#define BYTE_NUM 5
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#define RD_DESKEW_NUM 128
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#define WR_DESKEW_NUM 256
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#define LP4_WIDTH_REF_MHZ_H 1560
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#define LP4_RD_WIDTH_REF_H 25
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#define LP4_WR_WIDTH_REF_H 24
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#define LP4_WIDTH_REF_MHZ_L 1184
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#define LP4_RD_WIDTH_REF_L 30
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#define LP4_WR_WIDTH_REF_L 29
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#define DDR4_WIDTH_REF_MHZ_H 1560
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#define DDR4_RD_WIDTH_REF_H 30
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#define DDR4_WR_WIDTH_REF_H 22
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#define DDR4_WIDTH_REF_MHZ_L 1184
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#define DDR4_RD_WIDTH_REF_L 32
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#define DDR4_WR_WIDTH_REF_L 26
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#define LP3_WIDTH_REF_MHZ_H 1184
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#define LP3_RD_WIDTH_REF_H 34
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#define LP3_WR_WIDTH_REF_H 25
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#define LP3_WIDTH_REF_MHZ_L 920
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#define LP3_RD_WIDTH_REF_L 39
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#define LP3_WR_WIDTH_REF_L 28
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#define DDR3_WIDTH_REF_MHZ_H 1184
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#define DDR3_RD_WIDTH_REF_H 32
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#define DDR3_WR_WIDTH_REF_H 31
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#define DDR3_WIDTH_REF_MHZ_L 920
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#define DDR3_RD_WIDTH_REF_L 39
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#define DDR3_WR_WIDTH_REF_L 34
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#endif /* _ASM_ARCH_SDRAM_RK3568_H */
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