/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_RK3308_H
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#define _ASM_ARCH_SDRAM_RK3308_H
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#include <ram.h>
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#include <asm/arch/cru_rk3308.h>
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#include <asm/arch/grf_rk3308.h>
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#include <asm/arch/pmu_rk3308.h>
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#include <asm/arch/sdram_common.h>
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#include <asm/arch/sdram_rv1108_pctl_phy.h>
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#define CG_EXIT_TH (250)
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#define PATTERN (0x5aa5f00f)
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struct rk3308_ddr_standby {
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u32 con0;
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u32 con1;
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u32 status0;
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};
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struct rk3308_service_msch {
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u32 id_coreid;
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u32 id_revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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};
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enum {
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/* ddr standby */
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IDLE_TH_SHIFT = 16,
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/* can not gate msch clk */
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MSCH_GATE_CLK_SHIFT = 7,
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MSCH_GATE_CLK_EN = 1,
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DDRPHY4X_GATE_SHIFT = 6,
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DDRPHY4X_GATE_EN = 1,
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UPCTL_CORE_CLK_GATE_SHIFT = 5,
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UPCTL_CORE_CLK_GATE_EN = 1,
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UPCTL_ACLK_GATE_SHIFT = 4,
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UPCTL_ACLK_GATE_EN = 1,
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CTL_IDLR_SHIFT = 1,
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CTL_IDLR_EN = 1,
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STDBY_EN_SHIFT = 0,
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STDBY_EN = 1,
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CG_EXIT_TH_SHIFT = 16,
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STDBY_STATUS_SHIFT = 0,
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STDBY_STATUS_MASK = 0x7f << STDBY_STATUS_SHIFT,
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ST_STDBY = 0x10,
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};
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enum {
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/* memory scheduler ddrtiming */
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BWRATIO_HALF_BW = 0x80000000,
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BWRATIO_HALF_BW_DIS = 0x0,
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PHY_TX_DE_SKEW_SHIFT = 3,
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PHY_TX_DE_SKEW_EN = 1,
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};
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struct dram_info {
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struct rk3308_cru *cru;
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struct rk3308_grf *grf;
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struct rk3308_sgrf *sgrf;
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struct rk3308_pmu *pmu;
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struct ddr_phy *phy;
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struct ddr_pctl *pctl;
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struct rk3308_ddr_standby *standby;
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struct rk3308_service_msch *service_msch;
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struct ram_info info;
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};
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struct sdram_params {
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u32 idle_pd;
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u32 idle_sr;
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u32 ddr_2t_en;
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u32 stdby_idle;
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struct ddr_config ddr_config_t;
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struct ddr_timing ddr_timing_t;
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};
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struct rk3308_ddr_skew {
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u32 a0_a1_skew[14];
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u32 cs0_dm0_skew[22];
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};
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struct rk3308_ddr_gd {
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struct sdram_head_info_v0 head_info;
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struct rk3308_ddr_skew ddr_skew;
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};
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int check_rd_gate(struct dram_info *priv);
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void copy_to_reg(u32 *dest, const u32 *src, u32 n);
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void enable_low_power(struct dram_info *priv,
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struct sdram_params *params_priv);
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void ddr_cap_info(size_t size);
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void ddr_msch_cfg(struct dram_info *priv,
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struct sdram_params *params_priv);
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void ddr_msch_cfg_rbc(struct sdram_params *params_priv,
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struct dram_info *priv);
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void ddr_msch_get_max_col(struct dram_info *priv,
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struct ddr_schedule *sch_priv);
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void ddr_msch_get_max_row(struct dram_info *priv,
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struct ddr_schedule *sch_priv);
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void ddr_phy_skew_cfg(struct dram_info *priv);
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void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq);
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void enable_ddr_io_ret(struct dram_info *priv);
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void modify_data_training(struct dram_info *priv,
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struct sdram_params *params_priv);
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void move_to_config_state(struct dram_info *priv);
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void move_to_access_state(struct dram_info *priv);
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void pctl_cfg_grf(struct dram_info *priv,
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struct sdram_params *params_priv);
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void phy_pctrl_reset_cru(struct dram_info *priv);
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void print_dec(u32 n);
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void rkdclk_init(struct dram_info *priv,
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struct sdram_params *params_priv);
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int rv1108_sdram_init(struct dram_info *sdram_priv,
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struct sdram_params *params_priv);
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void set_bw_grf(struct dram_info *priv);
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void set_ds_odt(struct dram_info *priv,
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struct sdram_params *params_priv);
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#endif
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