/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_IOC_RK3528_H
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#define _ASM_ARCH_IOC_RK3528_H
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#include <common.h>
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struct rk3528_gpio0_ioc {
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uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
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uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
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uint32_t reserved0008[62]; /* Address Offset: 0x0008 */
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uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */
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uint32_t reserved010c[61]; /* Address Offset: 0x010C */
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uint32_t gpio0a_pull; /* Address Offset: 0x0200 */
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uint32_t reserved0204[63]; /* Address Offset: 0x0204 */
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uint32_t gpio0a_ie; /* Address Offset: 0x0300 */
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uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
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uint32_t gpio0a_smt; /* Address Offset: 0x0400 */
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uint32_t reserved0404[63]; /* Address Offset: 0x0404 */
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uint32_t gpio0a_sus; /* Address Offset: 0x0500 */
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uint32_t reserved0504[63]; /* Address Offset: 0x0504 */
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uint32_t gpio0a_sl; /* Address Offset: 0x0600 */
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uint32_t reserved0604[63]; /* Address Offset: 0x0604 */
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uint32_t gpio0a_od; /* Address Offset: 0x0700 */
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uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */
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};
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check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704);
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struct rk3528_gpio1_ioc {
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uint32_t reserved0000[8]; /* Address Offset: 0x0000 */
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uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
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uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
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uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
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uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
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uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
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uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
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uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
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uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
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uint32_t reserved0040[56]; /* Address Offset: 0x0040 */
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uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */
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uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */
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uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */
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uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */
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uint32_t reserved0160[44]; /* Address Offset: 0x0160 */
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uint32_t gpio1a_pull; /* Address Offset: 0x0210 */
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uint32_t gpio1b_pull; /* Address Offset: 0x0214 */
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uint32_t gpio1c_pull; /* Address Offset: 0x0218 */
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uint32_t gpio1d_pull; /* Address Offset: 0x021C */
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uint32_t reserved0220[60]; /* Address Offset: 0x0220 */
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uint32_t gpio1a_ie; /* Address Offset: 0x0310 */
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uint32_t gpio1b_ie; /* Address Offset: 0x0314 */
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uint32_t gpio1c_ie; /* Address Offset: 0x0318 */
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uint32_t gpio1d_ie; /* Address Offset: 0x031C */
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uint32_t reserved0320[60]; /* Address Offset: 0x0320 */
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uint32_t gpio1a_smt; /* Address Offset: 0x0410 */
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uint32_t gpio1b_smt; /* Address Offset: 0x0414 */
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uint32_t gpio1c_smt; /* Address Offset: 0x0418 */
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uint32_t gpio1d_smt; /* Address Offset: 0x041C */
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uint32_t reserved0420[60]; /* Address Offset: 0x0420 */
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uint32_t gpio1a_sus; /* Address Offset: 0x0510 */
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uint32_t gpio1b_sus; /* Address Offset: 0x0514 */
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uint32_t gpio1c_sus; /* Address Offset: 0x0518 */
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uint32_t gpio1d_sus; /* Address Offset: 0x051C */
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uint32_t reserved0520[60]; /* Address Offset: 0x0520 */
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uint32_t gpio1a_sl; /* Address Offset: 0x0610 */
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uint32_t gpio1b_sl; /* Address Offset: 0x0614 */
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uint32_t gpio1c_sl; /* Address Offset: 0x0618 */
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uint32_t gpio1d_sl; /* Address Offset: 0x061C */
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uint32_t reserved0620[60]; /* Address Offset: 0x0620 */
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uint32_t gpio1a_od; /* Address Offset: 0x0710 */
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uint32_t gpio1b_od; /* Address Offset: 0x0714 */
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uint32_t gpio1c_od; /* Address Offset: 0x0718 */
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uint32_t gpio1d_od; /* Address Offset: 0x071C */
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uint32_t reserved0720[60]; /* Address Offset: 0x0720 */
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uint32_t vccio0_poc; /* Address Offset: 0x0810 */
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uint32_t reserved0814[3]; /* Address Offset: 0x0814 */
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uint32_t vccio1_poc; /* Address Offset: 0x0820 */
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};
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check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820);
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struct rk3528_gpio2_ioc {
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uint32_t reserved0000[16]; /* Address Offset: 0x0000 */
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uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
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uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
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uint32_t reserved0048[70]; /* Address Offset: 0x0048 */
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uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */
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uint32_t reserved0170[44]; /* Address Offset: 0x0170 */
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uint32_t gpio2a_pull; /* Address Offset: 0x0220 */
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uint32_t reserved0224[63]; /* Address Offset: 0x0224 */
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uint32_t gpio2a_ie; /* Address Offset: 0x0320 */
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uint32_t reserved0324[63]; /* Address Offset: 0x0324 */
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uint32_t gpio2a_smt; /* Address Offset: 0x0420 */
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uint32_t reserved0424[63]; /* Address Offset: 0x0424 */
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uint32_t gpio2a_sus; /* Address Offset: 0x0520 */
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uint32_t reserved0524[63]; /* Address Offset: 0x0524 */
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uint32_t gpio2a_sl; /* Address Offset: 0x0620 */
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uint32_t reserved0624[63]; /* Address Offset: 0x0624 */
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uint32_t gpio2a_od; /* Address Offset: 0x0720 */
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uint32_t reserved0724[67]; /* Address Offset: 0x0724 */
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uint32_t vccio2_poc; /* Address Offset: 0x0830 */
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};
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check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830);
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struct rk3528_gpio3_ioc {
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uint32_t reserved0000[24]; /* Address Offset: 0x0000 */
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uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
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uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
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uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
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uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
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uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
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uint32_t reserved0074[71]; /* Address Offset: 0x0074 */
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uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */
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uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */
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uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */
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uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */
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uint32_t gpio3a_pull; /* Address Offset: 0x0230 */
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uint32_t gpio3b_pull; /* Address Offset: 0x0234 */
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uint32_t gpio3c_pull; /* Address Offset: 0x0238 */
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uint32_t reserved023c[61]; /* Address Offset: 0x023C */
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uint32_t gpio3a_ie; /* Address Offset: 0x0330 */
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uint32_t gpio3b_ie; /* Address Offset: 0x0334 */
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uint32_t gpio3c_ie; /* Address Offset: 0x0338 */
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uint32_t reserved033c[61]; /* Address Offset: 0x033C */
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uint32_t gpio3a_smt; /* Address Offset: 0x0430 */
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uint32_t gpio3b_smt; /* Address Offset: 0x0434 */
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uint32_t gpio3c_smt; /* Address Offset: 0x0438 */
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uint32_t reserved043c[61]; /* Address Offset: 0x043C */
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uint32_t gpio3a_sus; /* Address Offset: 0x0530 */
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uint32_t gpio3b_sus; /* Address Offset: 0x0534 */
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uint32_t gpio3c_sus; /* Address Offset: 0x0538 */
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uint32_t reserved053c[61]; /* Address Offset: 0x053C */
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uint32_t gpio3a_sl; /* Address Offset: 0x0630 */
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uint32_t gpio3b_sl; /* Address Offset: 0x0634 */
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uint32_t gpio3c_sl; /* Address Offset: 0x0638 */
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uint32_t reserved063c[61]; /* Address Offset: 0x063C */
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uint32_t gpio3a_od; /* Address Offset: 0x0730 */
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uint32_t gpio3b_od; /* Address Offset: 0x0734 */
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uint32_t gpio3c_od; /* Address Offset: 0x0738 */
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uint32_t reserved073c[65]; /* Address Offset: 0x073C */
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uint32_t vccio3_poc; /* Address Offset: 0x0840 */
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};
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check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840);
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struct rk3528_gpio4_ioc {
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uint32_t reserved0000[32]; /* Address Offset: 0x0000 */
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uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
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uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
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uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
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uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
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uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
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uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
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uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
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uint32_t reserved009c[73]; /* Address Offset: 0x009C */
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uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */
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uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */
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uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */
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uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */
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uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */
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uint32_t gpio4a_pull; /* Address Offset: 0x0240 */
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uint32_t gpio4b_pull; /* Address Offset: 0x0244 */
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uint32_t gpio4c_pull; /* Address Offset: 0x0248 */
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uint32_t gpio4d_pull; /* Address Offset: 0x024C */
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uint32_t reserved0250[60]; /* Address Offset: 0x0250 */
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uint32_t gpio4a_ie; /* Address Offset: 0x0340 */
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uint32_t gpio4b_ie; /* Address Offset: 0x0344 */
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uint32_t gpio4c_ie; /* Address Offset: 0x0348 */
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uint32_t gpio4d_ie; /* Address Offset: 0x034C */
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uint32_t reserved0350[60]; /* Address Offset: 0x0350 */
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uint32_t gpio4a_smt; /* Address Offset: 0x0440 */
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uint32_t gpio4b_smt; /* Address Offset: 0x0444 */
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uint32_t gpio4c_smt; /* Address Offset: 0x0448 */
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uint32_t gpio4d_smt; /* Address Offset: 0x044C */
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uint32_t reserved0450[60]; /* Address Offset: 0x0450 */
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uint32_t gpio4a_sus; /* Address Offset: 0x0540 */
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uint32_t gpio4b_sus; /* Address Offset: 0x0544 */
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uint32_t gpio4c_sus; /* Address Offset: 0x0548 */
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uint32_t gpio4d_sus; /* Address Offset: 0x054C */
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uint32_t reserved0550[60]; /* Address Offset: 0x0550 */
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uint32_t gpio4a_sl; /* Address Offset: 0x0640 */
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uint32_t gpio4b_sl; /* Address Offset: 0x0644 */
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uint32_t gpio4c_sl; /* Address Offset: 0x0648 */
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uint32_t gpio4d_sl; /* Address Offset: 0x064C */
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uint32_t reserved0650[60]; /* Address Offset: 0x0650 */
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uint32_t gpio4a_od; /* Address Offset: 0x0740 */
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uint32_t gpio4b_od; /* Address Offset: 0x0744 */
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uint32_t gpio4c_od; /* Address Offset: 0x0748 */
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uint32_t gpio4d_od; /* Address Offset: 0x074C */
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uint32_t reserved0750[64]; /* Address Offset: 0x0750 */
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uint32_t vccio4_poc; /* Address Offset: 0x0850 */
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};
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check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850);
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#endif
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