/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_I2C_H
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#define __ASM_ARCH_I2C_H
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struct i2c_regs {
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u32 con;
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u32 clkdiv;
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u32 mrxaddr;
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u32 mrxraddr;
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u32 mtxcnt;
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u32 mrxcnt;
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u32 ien;
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u32 ipd;
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u32 fcnt;
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u32 reserved0[0x37];
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u32 txdata[8];
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u32 reserved1[0x38];
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u32 rxdata[8];
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};
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/* Control register */
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#define I2C_CON_EN (1 << 0)
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#define I2C_CON_MOD(mod) ((mod) << 1)
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#define I2C_MODE_TX 0x00
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#define I2C_MODE_TRX 0x01
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#define I2C_MODE_RX 0x02
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#define I2C_MODE_RRX 0x03
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#define I2C_CON_MASK (3 << 1)
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#define I2C_CON_START (1 << 3)
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#define I2C_CON_STOP (1 << 4)
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#define I2C_CON_LASTACK (1 << 5)
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#define I2C_CON_ACTACK (1 << 6)
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#define I2C_CON_TUNING_MASK (0xff << 8)
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#define I2C_CON_SDA_CFG(cfg) ((cfg) << 8)
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#define I2C_CON_STA_CFG(cfg) ((cfg) << 12)
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#define I2C_CON_STO_CFG(cfg) ((cfg) << 14)
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#define I2C_CON_VERSION GENMASK_ULL(24, 16)
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#define I2C_CON_VERSION_SHIFT 16
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/* Clock dividor register */
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#define I2C_CLK_DIV_HIGH_SHIFT 16
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#define I2C_CLKDIV_VAL(divl, divh) \
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(((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
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/* the slave address accessed for master rx mode */
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#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr))
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/* the slave register address accessed for master rx mode */
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#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr))
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/* interrupt enable register */
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#define I2C_BTFIEN (1 << 0)
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#define I2C_BRFIEN (1 << 1)
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#define I2C_MBTFIEN (1 << 2)
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#define I2C_MBRFIEN (1 << 3)
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#define I2C_STARTIEN (1 << 4)
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#define I2C_STOPIEN (1 << 5)
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#define I2C_NAKRCVIEN (1 << 6)
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/* interrupt pending register */
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#define I2C_BTFIPD (1 << 0)
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#define I2C_BRFIPD (1 << 1)
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#define I2C_MBTFIPD (1 << 2)
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#define I2C_MBRFIPD (1 << 3)
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#define I2C_STARTIPD (1 << 4)
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#define I2C_STOPIPD (1 << 5)
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#define I2C_NAKRCVIPD (1 << 6)
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#define I2C_IPD_ALL_CLEAN 0x7f
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#endif
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