/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3588_H
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#define _ASM_ARCH_GRF_RK3588_H
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#include <common.h>
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struct rk3588_sys_grf {
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uint32_t wdt_con0; /* Address Offset: 0x0000 */
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uint32_t reserved0004[3]; /* Address Offset: 0x0004 */
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uint32_t uart_con0; /* Address Offset: 0x0010 */
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uint32_t uart_con1; /* Address Offset: 0x0014 */
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uint32_t reserved0018[42]; /* Address Offset: 0x0018 */
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uint32_t gic_con0; /* Address Offset: 0x00C0 */
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uint32_t reserved00c4[79]; /* Address Offset: 0x00C4 */
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uint32_t memcfg_con0; /* Address Offset: 0x0200 */
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uint32_t memcfg_con1; /* Address Offset: 0x0204 */
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uint32_t memcfg_con2; /* Address Offset: 0x0208 */
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uint32_t memcfg_con3; /* Address Offset: 0x020C */
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uint32_t memcfg_con4; /* Address Offset: 0x0210 */
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uint32_t memcfg_con5; /* Address Offset: 0x0214 */
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uint32_t memcfg_con6; /* Address Offset: 0x0218 */
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uint32_t memcfg_con7; /* Address Offset: 0x021C */
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uint32_t memcfg_con8; /* Address Offset: 0x0220 */
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uint32_t memcfg_con9; /* Address Offset: 0x0224 */
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uint32_t memcfg_con10; /* Address Offset: 0x0228 */
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uint32_t memcfg_con11; /* Address Offset: 0x022C */
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uint32_t memcfg_con12; /* Address Offset: 0x0230 */
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uint32_t memcfg_con13; /* Address Offset: 0x0234 */
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uint32_t memcfg_con14; /* Address Offset: 0x0238 */
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uint32_t memcfg_con15; /* Address Offset: 0x023C */
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uint32_t memcfg_con16; /* Address Offset: 0x0240 */
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uint32_t memcfg_con17; /* Address Offset: 0x0244 */
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uint32_t memcfg_con18; /* Address Offset: 0x0248 */
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uint32_t memcfg_con19; /* Address Offset: 0x024C */
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uint32_t memcfg_con20; /* Address Offset: 0x0250 */
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uint32_t memcfg_con21; /* Address Offset: 0x0254 */
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uint32_t memcfg_con22; /* Address Offset: 0x0258 */
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uint32_t memcfg_con23; /* Address Offset: 0x025C */
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uint32_t memcfg_con24; /* Address Offset: 0x0260 */
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uint32_t reserved0264; /* Address Offset: 0x0264 */
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uint32_t memcfg_con26; /* Address Offset: 0x0268 */
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uint32_t memcfg_con27; /* Address Offset: 0x026C */
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uint32_t memcfg_con28; /* Address Offset: 0x0270 */
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uint32_t memcfg_con29; /* Address Offset: 0x0274 */
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uint32_t memcfg_con30; /* Address Offset: 0x0278 */
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uint32_t memcfg_con31; /* Address Offset: 0x027C */
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uint32_t reserved0280[33]; /* Address Offset: 0x0280 */
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uint32_t soc_con1; /* Address Offset: 0x0304 */
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uint32_t soc_con2; /* Address Offset: 0x0308 */
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uint32_t soc_con3; /* Address Offset: 0x030C */
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uint32_t reserved0310[2]; /* Address Offset: 0x0310 */
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uint32_t soc_con6; /* Address Offset: 0x0318 */
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uint32_t soc_con7; /* Address Offset: 0x031C */
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uint32_t soc_con8; /* Address Offset: 0x0320 */
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uint32_t soc_con9; /* Address Offset: 0x0324 */
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uint32_t soc_con10; /* Address Offset: 0x0328 */
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uint32_t soc_con11; /* Address Offset: 0x032C */
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uint32_t soc_con12; /* Address Offset: 0x0330 */
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uint32_t soc_con13; /* Address Offset: 0x0334 */
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uint32_t reserved0338[18]; /* Address Offset: 0x0338 */
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uint32_t soc_status0; /* Address Offset: 0x0380 */
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uint32_t soc_status1; /* Address Offset: 0x0384 */
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uint32_t soc_status2; /* Address Offset: 0x0388 */
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uint32_t soc_status3; /* Address Offset: 0x038C */
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uint32_t reserved0390[92]; /* Address Offset: 0x0390 */
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uint32_t otp_key08; /* Address Offset: 0x0500 */
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uint32_t otp_key0d; /* Address Offset: 0x0504 */
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uint32_t otp_key0e; /* Address Offset: 0x0508 */
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uint32_t reserved050c[61]; /* Address Offset: 0x050C */
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uint32_t chip_id; /* Address Offset: 0x0600 */
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};
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check_member(rk3588_sys_grf, chip_id, 0x0600);
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struct rk3588_php_grf {
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uint32_t php_con0; /* Address Offset: 0x0000 */
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uint32_t php_con1; /* Address Offset: 0x0004 */
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uint32_t gmac_con0; /* Address Offset: 0x0008 */
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uint32_t reserved000c; /* Address Offset: 0x000C */
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uint32_t sata_con0; /* Address Offset: 0x0010 */
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uint32_t sata_con1; /* Address Offset: 0x0014 */
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uint32_t sata_con2; /* Address Offset: 0x0018 */
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uint32_t php_mmu_con0; /* Address Offset: 0x001C */
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uint32_t php_mmu_con1; /* Address Offset: 0x0020 */
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uint32_t php_mmu_con2; /* Address Offset: 0x0024 */
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uint32_t its_taddr0; /* Address Offset: 0x0028 */
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uint32_t its_taddr1; /* Address Offset: 0x002C */
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uint32_t pcie_mmu_pciemode; /* Address Offset: 0x0030 */
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uint32_t pcie_mmu_con0; /* Address Offset: 0x0034 */
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uint32_t pcie_mmu_con1; /* Address Offset: 0x0038 */
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uint32_t pcie_mmu_con2; /* Address Offset: 0x003C */
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uint32_t mem_con0; /* Address Offset: 0x0040 */
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uint32_t php_st0; /* Address Offset: 0x0044 */
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uint32_t php_st1; /* Address Offset: 0x0048 */
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uint32_t php_st2; /* Address Offset: 0x004C */
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uint32_t php_st3; /* Address Offset: 0x0050 */
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uint32_t php_st4; /* Address Offset: 0x0054 */
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uint32_t mmu_pmu_ack; /* Address Offset: 0x0058 */
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uint32_t pcie_mmu_con6; /* Address Offset: 0x005C */
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uint32_t pcie_mmu_con7; /* Address Offset: 0x0060 */
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uint32_t mem_con5; /* Address Offset: 0x0064 */
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uint32_t mem_con10; /* Address Offset: 0x0068 */
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uint32_t reserved006c; /* Address Offset: 0x006C */
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uint32_t clk_con1; /* Address Offset: 0x0070 */
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uint32_t gmac0_sid_aw; /* Address Offset: 0x0074 */
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uint32_t gmac0_ssid_aw; /* Address Offset: 0x0078 */
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uint32_t gmac1_sid_aw; /* Address Offset: 0x007C */
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uint32_t gmac1_ssid_aw; /* Address Offset: 0x0080 */
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uint32_t sata0_sid_aw; /* Address Offset: 0x0084 */
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uint32_t sata0_ssid_aw; /* Address Offset: 0x0088 */
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uint32_t sata1_sid_aw; /* Address Offset: 0x008C */
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uint32_t sata1_ssid_aw; /* Address Offset: 0x0090 */
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uint32_t sata2_sid_aw; /* Address Offset: 0x0094 */
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uint32_t sata2_ssid_aw; /* Address Offset: 0x0098 */
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uint32_t gmac0_sid_ar; /* Address Offset: 0x009C */
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uint32_t gmac0_ssid_ar; /* Address Offset: 0x00A0 */
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uint32_t gmac1_sid_ar; /* Address Offset: 0x00A4 */
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uint32_t gmac1_ssid_ar; /* Address Offset: 0x00A8 */
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uint32_t sata0_sid_ar; /* Address Offset: 0x00AC */
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uint32_t sata0_ssid_ar; /* Address Offset: 0x00B0 */
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uint32_t sata1_sid_ar; /* Address Offset: 0x00B4 */
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uint32_t sata1_ssid_ar; /* Address Offset: 0x00B8 */
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uint32_t sata2_sid_ar; /* Address Offset: 0x00BC */
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uint32_t sata2_ssid_ar; /* Address Offset: 0x00C0 */
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uint32_t usb3otg_2_sid_ar; /* Address Offset: 0x00C4 */
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uint32_t usb3otg_2_ssid_ar; /* Address Offset: 0x00C8 */
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uint32_t usb3otg_2_sid_aw; /* Address Offset: 0x00CC */
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uint32_t usb3otg_2_ssid_aw; /* Address Offset: 0x00D0 */
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uint32_t gmac_con_pst; /* Address Offset: 0x00D4 */
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uint32_t gmac0_cmd; /* Address Offset: 0x00D8 */
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uint32_t gmac1_cmd; /* Address Offset: 0x00DC */
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uint32_t mem_con11; /* Address Offset: 0x00E0 */
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uint32_t usb3otg_2_con0; /* Address Offset: 0x00E4 */
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uint32_t usb3otg_2_con1; /* Address Offset: 0x00E8 */
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uint32_t usb3otg_2_intcon; /* Address Offset: 0x00EC */
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uint32_t usb3otg_2_st_lat0; /* Address Offset: 0x00F0 */
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uint32_t usb3otg_2_st_lat1; /* Address Offset: 0x00F4 */
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uint32_t usb3otg_2_st_cb; /* Address Offset: 0x00F8 */
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uint32_t usb3otg_2_st; /* Address Offset: 0x00FC */
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uint32_t pciesel_con; /* Address Offset: 0x0100 */
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uint32_t utmi_con; /* Address Offset: 0x0104 */
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uint32_t reserved0108; /* Address Offset: 0x0108 */
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uint32_t pcie4l_sid_aw; /* Address Offset: 0x010C */
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uint32_t pcie4l_sid_ar; /* Address Offset: 0x0110 */
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uint32_t pcie2l_sid_aw; /* Address Offset: 0x0114 */
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uint32_t pcie2l_sid_ar; /* Address Offset: 0x0118 */
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uint32_t pcie1l0_sid_aw; /* Address Offset: 0x011C */
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uint32_t pcie1l0_sid_ar; /* Address Offset: 0x0120 */
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uint32_t pcie1l1_sid_aw; /* Address Offset: 0x0124 */
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uint32_t pcie1l1_sid_ar; /* Address Offset: 0x0128 */
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uint32_t pcie1l2_sid_aw; /* Address Offset: 0x012C */
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uint32_t pcie1l2_sid_ar; /* Address Offset: 0x0130 */
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uint32_t reserved0134; /* Address Offset: 0x0134 */
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uint32_t pcie_ats; /* Address Offset: 0x0138 */
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uint32_t st_utmi; /* Address Offset: 0x013C */
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uint32_t reserved0140; /* Address Offset: 0x0140 */
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uint32_t pcie4l_ssid_aw; /* Address Offset: 0x0144 */
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uint32_t pcie4l_ssid_ar; /* Address Offset: 0x0148 */
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uint32_t pcie2l_ssid_aw; /* Address Offset: 0x014C */
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uint32_t pcie2l_ssid_ar; /* Address Offset: 0x0150 */
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uint32_t pcie1l0_ssid_aw; /* Address Offset: 0x0154 */
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uint32_t pcie1l0_ssid_ar; /* Address Offset: 0x0158 */
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uint32_t pcie1l1_ssid_aw; /* Address Offset: 0x015C */
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uint32_t pcie1l1_ssid_ar; /* Address Offset: 0x0160 */
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uint32_t pcie1l2_ssid_aw; /* Address Offset: 0x0164 */
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uint32_t pcie1l2_ssid_ar; /* Address Offset: 0x0168 */
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uint32_t pcie_ssid_v; /* Address Offset: 0x016C */
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uint32_t reserved0170; /* Address Offset: 0x0170 */
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uint32_t sata_pd_sel; /* Address Offset: 0x0174 */
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uint32_t pcie_mmu_irq_clr; /* Address Offset: 0x0178 */
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uint32_t php_mmu_irq_clr; /* Address Offset: 0x017C */
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uint32_t pcie_mmu_st; /* Address Offset: 0x0180 */
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uint32_t php_mmu_st; /* Address Offset: 0x0184 */
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uint32_t reserved0188; /* Address Offset: 0x0188 */
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uint32_t php_st0b; /* Address Offset: 0x018C */
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};
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check_member(rk3588_php_grf, php_st0b, 0x018c);
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#endif
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