/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3528_H
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#define _ASM_ARCH_GRF_RK3528_H
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#include <common.h>
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struct rk3528_grf {
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uint32_t reserved0[0x40018 / 4];
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/* vpugrf*/
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uint32_t gmac1_con0; /* Address Offset: 0x40018 */
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uint32_t gmac1_con1; /* Address Offset: 0x4001c */
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uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1];
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/* vogrf */
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uint32_t gmac0_con; /* Address Offset: 0x60018 */
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uint32_t macphy_con0; /* Address Offset: 0x6001c */
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uint32_t macphy_con1; /* Address Offset: 0x60020 */
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uint32_t sdmmc_con0; /* Address Offset: 0x60024 */
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uint32_t sdmmc_con1; /* Address Offset: 0x60028 */
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uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1];
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/* pmugrf */
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uint32_t soc_con[8]; /* Address Offset: 0x70000 */
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uint32_t soc_status; /* Address Offset: 0x70020 */
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uint32_t reserved3[3]; /* Address Offset: 0x70024 */
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uint32_t pmuio_vsel; /* Address Offset: 0x70030 */
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uint32_t reserved4[3]; /* Address Offset: 0x70034 */
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uint32_t mem_con; /* Address Offset: 0x70040 */
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uint32_t reserved5[47]; /* Address Offset: 0x70044 */
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uint32_t rstfunc_status; /* Address Offset: 0x70100 */
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uint32_t rstfunc_clr; /* Address Offset: 0x70104 */
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uint32_t reserved6[62]; /* Address Offset: 0x70108 */
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uint32_t os_reg0; /* Address Offset: 0x70200 */
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uint32_t os_reg1; /* Address Offset: 0x70204 */
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uint32_t os_reg2; /* Address Offset: 0x70208 */
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uint32_t os_reg3; /* Address Offset: 0x7020C */
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uint32_t os_reg4; /* Address Offset: 0x70210 */
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uint32_t os_reg5; /* Address Offset: 0x70214 */
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uint32_t os_reg6; /* Address Offset: 0x70218 */
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uint32_t os_reg7; /* Address Offset: 0x7021C */
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uint32_t os_reg8; /* Address Offset: 0x70220 */
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uint32_t os_reg9; /* Address Offset: 0x70224 */
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uint32_t os_reg10; /* Address Offset: 0x70228 */
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uint32_t os_reg11; /* Address Offset: 0x7022C */
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uint32_t os_reg12; /* Address Offset: 0x70230 */
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uint32_t os_reg13; /* Address Offset: 0x70234 */
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uint32_t os_reg14; /* Address Offset: 0x70238 */
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uint32_t os_reg15; /* Address Offset: 0x7023C */
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uint32_t os_reg16; /* Address Offset: 0x70240 */
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uint32_t os_reg17; /* Address Offset: 0x70244 */
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uint32_t os_reg18; /* Address Offset: 0x70248 */
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uint32_t os_reg19; /* Address Offset: 0x7024C */
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uint32_t os_reg20; /* Address Offset: 0x70250 */
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uint32_t os_reg21; /* Address Offset: 0x70254 */
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uint32_t os_reg22; /* Address Offset: 0x70258 */
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uint32_t os_reg23; /* Address Offset: 0x7025C */
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uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1];
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uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */
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uint32_t reserved8[2]; /* Address Offset: 0x80008 */
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uint32_t grf_sys_status; /* Address Offset: 0x80010 */
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uint32_t reserved9[3]; /* Address Offset: 0x80014 */
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uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */
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uint32_t reserved10[2]; /* Address Offset: 0x80028 */
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uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */
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uint32_t reserved11[17]; /* Address Offset: 0x8003C */
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uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */
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uint32_t reserved12[59]; /* Address Offset: 0x80094 */
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uint32_t grf_soc_code; /* Address Offset: 0x80180 */
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uint32_t reserved13[3]; /* Address Offset: 0x80184 */
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uint32_t grf_soc_version; /* Address Offset: 0x80190 */
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uint32_t reserved14[3]; /* Address Offset: 0x80194 */
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uint32_t grf_chip_id; /* Address Offset: 0x801A0 */
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uint32_t reserved15[3]; /* Address Offset: 0x801A4 */
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uint32_t grf_chip_version; /* Address Offset: 0x801B0 */
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uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1];
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};
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check_member(rk3528_grf, sdmmc_con1, 0x60028);
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check_member(rk3528_grf, os_reg23, 0x7025C);
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check_member(rk3528_grf, grf_chip_version, 0x801B0);
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#endif
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