/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_rk3308_H
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#define _ASM_ARCH_GRF_rk3308_H
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#include <common.h>
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struct rk3308_grf {
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unsigned int gpio0a_iomux;
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unsigned int reserved0;
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unsigned int gpio0b_iomux;
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unsigned int reserved1;
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unsigned int gpio0c_iomux;
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unsigned int reserved2[3];
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unsigned int gpio1a_iomux;
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unsigned int reserved3;
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unsigned int gpio1bl_iomux;
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unsigned int gpio1bh_iomux;
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unsigned int gpio1cl_iomux;
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unsigned int gpio1ch_iomux;
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unsigned int gpio1d_iomux;
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unsigned int reserved4;
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unsigned int gpio2a_iomux;
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unsigned int reserved5;
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unsigned int gpio2b_iomux;
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unsigned int reserved6;
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unsigned int gpio2c_iomux;
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unsigned int reserved7[3];
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unsigned int gpio3a_iomux;
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unsigned int reserved8;
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unsigned int gpio3b_iomux;
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unsigned int reserved9[5];
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unsigned int gpio4a_iomux;
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unsigned int reserved33;
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unsigned int gpio4b_iomux;
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unsigned int reserved10;
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unsigned int gpio4c_iomux;
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unsigned int reserved11;
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unsigned int gpio4d_iomux;
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unsigned int reserved34;
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unsigned int gpio0a_p;
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unsigned int gpio0b_p;
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unsigned int gpio0c_p;
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unsigned int reserved12;
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unsigned int gpio1a_p;
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unsigned int gpio1b_p;
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unsigned int gpio1c_p;
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unsigned int gpio1d_p;
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unsigned int gpio2a_p;
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unsigned int gpio2b_p;
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unsigned int gpio2c_p;
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unsigned int reserved13;
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unsigned int gpio3a_p;
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unsigned int gpio3b_p;
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unsigned int reserved14[2];
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unsigned int gpio4a_p;
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unsigned int gpio4b_p;
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unsigned int gpio4c_p;
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unsigned int gpio4d_p;
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unsigned int reserved15[(0x100 - 0xec) / 4 - 1];
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unsigned int gpio0a_e;
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unsigned int gpio0b_e;
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unsigned int gpio0c_e;
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unsigned int reserved16;
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unsigned int gpio1a_e;
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unsigned int gpio1b_e;
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unsigned int gpio1c_e;
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unsigned int gpio1d_e;
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unsigned int gpio2a_e;
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unsigned int gpio2b_e;
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unsigned int gpio2c_e;
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unsigned int reserved17;
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unsigned int gpio3a_e;
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unsigned int gpio3b_e;
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unsigned int reserved18[2];
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unsigned int gpio4a_e;
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unsigned int gpio4b_e;
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unsigned int gpio4c_e;
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unsigned int gpio4d_e;
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unsigned int gpio0a_sr;
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unsigned int gpio0b_sr;
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unsigned int gpio0c_sr;
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unsigned int reserved19;
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unsigned int gpio1a_sr;
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unsigned int gpio1b_sr;
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unsigned int gpio1c_sr;
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unsigned int gpio1d_sr;
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unsigned int gpio2a_sr;
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unsigned int gpio2b_sr;
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unsigned int gpio2c_sr;
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unsigned int reserved20;
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unsigned int gpio3a_sr;
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unsigned int gpio3b_sr;
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unsigned int reserved21[2];
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unsigned int gpio4a_sr;
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unsigned int gpio4b_sr;
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unsigned int gpio4c_sr;
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unsigned int gpio4d_sr;
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unsigned int gpio0a_smt;
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unsigned int gpio0b_smt;
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unsigned int gpio0c_smt;
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unsigned int reserved22;
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unsigned int gpio1a_smt;
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unsigned int gpio1b_smt;
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unsigned int gpio1c_smt;
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unsigned int gpio1d_smt;
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unsigned int gpio2a_smt;
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unsigned int gpio2b_smt;
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unsigned int gpio2c_smt;
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unsigned int reserved23;
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unsigned int gpio3a_smt;
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unsigned int gpio3b_smt;
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unsigned int reserved35[2];
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unsigned int gpio4a_smt;
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unsigned int gpio4b_smt;
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unsigned int gpio4c_smt;
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unsigned int gpio4d_smt;
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unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1];
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unsigned int soc_con0;
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unsigned int soc_con1;
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unsigned int soc_con2;
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unsigned int soc_con3;
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unsigned int soc_con4;
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unsigned int soc_con5;
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unsigned int soc_con6;
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unsigned int soc_con7;
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unsigned int soc_con8;
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unsigned int soc_con9;
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unsigned int soc_con10;
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unsigned int reserved25[(0x380 - 0x328) / 4 - 1];
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unsigned int soc_status0;
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unsigned int reserved26[(0x400 - 0x380) / 4 - 1];
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unsigned int cpu_con0;
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unsigned int cpu_con1;
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unsigned int cpu_con2;
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unsigned int reserved27[(0x420 - 0x408) / 4 - 1];
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unsigned int cpu_status0;
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unsigned int cpu_status1;
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unsigned int reserved28[(0x440 - 0x424) / 4 - 1];
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unsigned int pvtm_con0;
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unsigned int pvtm_con1;
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unsigned int pvtm_status0;
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unsigned int pvtm_status1;
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unsigned int reserved29[(0x460 - 0x44C) / 4 - 1];
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unsigned int tsadc_tbl;
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unsigned int tsadc_tbh;
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unsigned int reserved30[(0x480 - 0x464) / 4 - 1];
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unsigned int host0_con0;
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unsigned int host0_con1;
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unsigned int otg_con0;
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unsigned int host0_status0;
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unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1];
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unsigned int mac_con0;
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unsigned int upctl_con0;
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unsigned int upctl_status0;
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unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1];
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unsigned int os_reg0;
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unsigned int os_reg1;
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unsigned int os_reg2;
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unsigned int os_reg3;
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unsigned int os_reg4;
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unsigned int os_reg5;
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unsigned int os_reg6;
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unsigned int os_reg7;
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unsigned int os_reg8;
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unsigned int os_reg9;
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unsigned int os_reg10;
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unsigned int os_reg11;
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unsigned int reserved38[(0x600 - 0x52c) / 4 - 1];
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unsigned int soc_con12;
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unsigned int reserved39;
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unsigned int soc_con13;
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unsigned int soc_con14;
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unsigned int soc_con15;
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unsigned int reserved40[(0x800 - 0x610) / 4 - 1];
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unsigned int chip_id;
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};
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check_member(rk3308_grf, gpio0a_p, 0xa0);
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struct rk3308_sgrf {
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unsigned int soc_con0;
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unsigned int soc_con1;
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unsigned int con_tzma_r0size;
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unsigned int con_secure0;
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unsigned int reserved0;
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unsigned int clk_timer_en;
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unsigned int clkgat_con;
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unsigned int fastboot_addr;
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unsigned int fastboot_en;
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unsigned int reserved1[(0x30 - 0x24) / 4];
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unsigned int srst_con;
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};
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check_member(rk3308_sgrf, fastboot_en, 0x20);
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enum {
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/* GPIO0B_IOMUX */
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GPIO0B_SEL_SHIFT = 0x0,
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GPIO0B_SEL_MASK = 0x3 << GPIO0B_SEL_SHIFT,
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/* GPIO1D_IOMUX */
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GPIO1D1_SEL_SHIFT = 2,
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GPIO1D1_SEL_MASK = 0x3 << GPIO1D1_SEL_SHIFT,
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GPIO1D1_SEL_UART1_TX = 1,
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GPIO1D0_SEL_SHIFT = 0,
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GPIO1D0_SEL_MASK = 0x3 << GPIO1D0_SEL_SHIFT,
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GPIO1D1_SEL_UART1_RX = 1,
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/* GPIO2A_IOMUX */
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GPIO2A1_SEL_SHIFT = 2,
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GPIO2A1_SEL_MASK = 0x3 << GPIO2A1_SEL_SHIFT,
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GPIO2A1_SEL_UART0_TX = 1,
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GPIO2A0_SEL_SHIFT = 0,
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GPIO2A0_SEL_MASK = 0x3 << GPIO2A0_SEL_SHIFT,
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GPIO2A0_SEL_UART0_RX = 1,
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/* GPIO3B_IOMUX */
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GPIO3B5_SEL_SHIFT = 12,
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GPIO3B5_SEL_MASK = 0xf << GPIO3B5_SEL_SHIFT,
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GPIO3B5_SEL_UART3_TX = 4,
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GPIO3B4_SEL_SHIFT = 8,
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GPIO3B4_SEL_MASK = 0xf << GPIO3B4_SEL_SHIFT,
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GPIO3B4_SEL_UART3_RX = 4,
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/* GPIO4B_IOMUX */
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GPIO4B1_SEL_SHIFT = 2,
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GPIO4B1_SEL_MASK = 0x3 << GPIO4B1_SEL_SHIFT,
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GPIO4B1_SEL_UART4_TX = 1,
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GPIO4B0_SEL_SHIFT = 0,
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GPIO4B0_SEL_MASK = 0x3 << GPIO4B0_SEL_SHIFT,
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GPIO4B0_SEL_UART4_RX = 1,
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/* GPIO4D_IOMUX */
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GPIO4D3_SEL_SHIFT = 6,
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GPIO4D3_SEL_MASK = 0x3 << GPIO4D3_SEL_SHIFT,
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GPIO4D3_SEL_UART2_TXM1 = 2,
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GPIO4D2_SEL_SHIFT = 4,
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GPIO4D2_SEL_MASK = 0x3 << GPIO4D2_SEL_SHIFT,
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GPIO4D2_SEL_UART2_RXM1 = 2,
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/* PVTM_CON0 */
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PVTM_PMU_OSC_EN_SHIFT = 1,
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PVTM_PMU_OSC_EN_MASK = 0x1 << PVTM_PMU_OSC_EN_SHIFT,
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PVTM_PMU_OSC_EN = 1,
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PVTM_PMU_START_SHIFT = 0,
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PVTM_PMU_START_MASK = 0x1 << PVTM_PMU_START_SHIFT,
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PVTM_PMU_START = 1,
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/* PVTM_CON1 */
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PVTM_PMU_CAL_CNT = 0x1234,
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/* PVTM_STATUS0 */
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PVTM_PMU_FREQ_DONE_SHIFT = 0,
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PVTM_PMU_FREQ_DONE_MASK = 0x1 << PVTM_PMU_FREQ_DONE_SHIFT,
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/* UPCTL_CON0 */
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CYSYREQ_UPCTL_DDRSTDBY_SHIFT = 5,
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CYSYREQ_UPCTL_DDRSTDBY_MASK = 1 << CYSYREQ_UPCTL_DDRSTDBY_SHIFT,
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CYSYREQ_UPCTL_DDRSTDBY_EN = 1,
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GRF_DDR_16BIT_EN_SHIFT = 0,
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GRF_DDR_16BIT_EN_MASK = 1 << GRF_DDR_16BIT_EN_SHIFT,
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GRF_DDR_16BIT_EN = 1,
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/* UPCTL_STATUS0 */
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DFI_SCRAMBLE_KEY_READY_SHIFT = 21,
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DFI_SCRAMBLE_KEY_READY_MASK = 0x1 << DFI_SCRAMBLE_KEY_READY_SHIFT,
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/* SOC_CON5 */
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UART2_MULTI_IOFUNC_SEL_SHIFT = 2,
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UART2_MULTI_IOFUNC_SEL_MASK = 0x3 << UART2_MULTI_IOFUNC_SEL_SHIFT,
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UART2_MULTI_IOFUNC_SEL_M1 = 1,
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/* SOC_CON12 */
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NOC_MSCH_MAIN_PARTIAL_SHIFT = 1,
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NOC_MSCH_MAIN_PARTIAL_MASK = 0x1 << NOC_MSCH_MAIN_PARTIAL_SHIFT,
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NOC_MSCH_MAIN_PARTIAL_EN = 1,
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NOC_MSCH_MAINDDR3_SHIFT = 0,
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NOC_MSCH_MAINDDR3_MASK = 0x1 << NOC_MSCH_MAINDDR3_SHIFT,
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NOC_MSCH_MAINDDR3_EN = 1,
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NOC_MSCH_MAINDDR3_DIS = 0,
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};
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enum { /* SGRF_CON0 */
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DDR_DFI_SCRAMBLE_EN_SHIFT = 13,
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DDR_DFI_SCRAMBLE_EN_MASK = 0x1 << DDR_DFI_SCRAMBLE_EN_SHIFT,
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DDR_DFI_SCRAMBLE_EN = 1,
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};
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#endif
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