/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RV1106_H
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#define _ASM_ARCH_CRU_RV1106_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#ifdef CONFIG_SPL_KERNEL_BOOT
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#define APLL_HZ (1104 * MHz)
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#else
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#define APLL_HZ (816 * MHz)
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#endif
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#define GPLL_HZ (1188 * MHz)
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#define CPLL_HZ (1000 * MHz)
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/* RV1106 pll id */
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enum rv1106_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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PLL_COUNT,
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};
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struct rv1106_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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struct rv1106_clk_priv {
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struct rv1106_cru *cru;
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struct rv1106_grf *grf;
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ulong gpll_hz;
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ulong cpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rv1106_grf_clk_priv {
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struct rv1106_grf *grf;
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};
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struct rv1106_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct rv1106_cru {
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unsigned int reserved0[192];
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unsigned int pmu_clksel_con[8];
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unsigned int reserved1[312];
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unsigned int pmu_clkgate_con[3];
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unsigned int reserved2[125];
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unsigned int pmu_softrst_con[3];
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unsigned int reserved3[15741];
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struct rv1106_pll pll[4];
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unsigned int reserved4[128];
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unsigned int mode;
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unsigned int reserved5[31];
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unsigned int clksel_con[34];
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unsigned int reserved6[286];
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unsigned int clkgate_con[4];
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unsigned int reserved7[124];
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unsigned int softrst_con[3];
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unsigned int reserved8[125];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int con[2];
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unsigned int sdmmc_con[2];
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unsigned int emmc_con[2];
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unsigned int reserved9[1461];
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unsigned int peri_clksel_con[12];
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unsigned int reserved10[308];
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unsigned int peri_clkgate_con[8];
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unsigned int reserved11[120];
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unsigned int peri_softrst_con[8];
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unsigned int reserved12[1592];
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unsigned int vi_clksel_con[4];
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unsigned int reserved13[316];
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unsigned int vi_clkgate_con[3];
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unsigned int reserved14[125];
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unsigned int vi_softrst_con[3];
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unsigned int reserved15[3645];
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unsigned int core_clksel_con[5];
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unsigned int reserved16[2043];
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unsigned int vepu_clksel_con[2];
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unsigned int reserved17[318];
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unsigned int vepu_clkgate_con[3];
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unsigned int reserved18[125];
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unsigned int vepu_softrst_con[2];
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unsigned int reserved19[1598];
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unsigned int vo_clksel_con[4];
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unsigned int reserved20[316];
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unsigned int vo_clkgate_con[3];
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unsigned int reserved21[125];
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unsigned int vo_softrst_con[4];
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};
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check_member(rv1106_cru, vo_softrst_con[0], 0x1ca00);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RV1106_TOPCRU_BASE 0x10000
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#define RV1106_SUBDDRCRU_BASE 0x1F000
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#define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
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#define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
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#define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
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enum {
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/* CRU_PMU_CLK_SEL0_CON */
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CLK_I2C1_SEL_SHIFT = 6,
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CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
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CLK_I2C1_SEL_200M = 0,
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CLK_I2C1_SEL_100M,
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CLK_I2C1_SEL_24M,
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CLK_I2C1_SEL_32K,
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HCLK_PMU_SEL_SHIFT = 4,
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HCLK_PMU_SEL_MASK = 0x3 << HCLK_PMU_SEL_SHIFT,
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HCLK_PMU_SEL_200M = 0,
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HCLK_PMU_SEL_100M,
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HCLK_PMU_SEL_24M,
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PCLK_PMU_SEL_SHIFT = 3,
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PCLK_PMU_SEL_MASK = 0x1 << PCLK_PMU_SEL_SHIFT,
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PCLK_PMU_SEL_100M = 0,
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PCLK_PMU_SEL_24M,
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/* CRU_CLK_SEL5_CON */
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CLK_UART_SRC_SEL_SHIFT = 5,
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CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
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CLK_UART_SRC_SEL_GPLL = 0,
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CLK_UART_SRC_SEL_CPLL,
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CLK_UART_SRC_DIV_SHIFT = 0,
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CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT,
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/* CRU_CLK_SEL6_CON */
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CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
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CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL7_CON */
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CLK_UART_SEL_SHIFT = 0,
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CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
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CLK_UART_SEL_SRC = 0,
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CLK_UART_SEL_FRAC,
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CLK_UART_SEL_XIN24M,
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/* CRU_CLK_SEL23_CON */
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DCLK_VOP_SEL_SHIFT = 8,
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DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_GPLL = 0,
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DCLK_VOP_SEL_CPLL,
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DCLK_VOP_DIV_SHIFT = 3,
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DCLK_VOP_DIV_MASK = 0x1f << DCLK_VOP_DIV_SHIFT,
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/* CRU_CLK_SEL24_CON */
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PCLK_TOP_SEL_SHIFT = 5,
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PCLK_TOP_SEL_MASK = 0x3 << PCLK_TOP_SEL_SHIFT,
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PCLK_TOP_SEL_100M = 0,
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PCLK_TOP_SEL_50M,
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PCLK_TOP_SEL_24M,
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/* CRU_PERI_CLK_SEL1_CON */
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CLK_I2C3_SEL_SHIFT = 14,
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CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
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CLK_I2C2_SEL_SHIFT = 12,
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CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
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CLK_I2C0_SEL_SHIFT = 8,
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CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
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CLK_I2C0_SEL_200M = 0,
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CLK_I2C0_SEL_100M,
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CLK_I2C0_SEL_50M,
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CLK_I2C0_SEL_24M,
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HCLK_PERI_SEL_SHIFT = 4,
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HCLK_PERI_SEL_MASK = 0x3 << HCLK_PERI_SEL_SHIFT,
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HCLK_PERI_SEL_200M = 0,
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HCLK_PERI_SEL_100M,
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HCLK_PERI_SEL_50M,
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HCLK_PERI_SEL_24M,
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ACLK_PERI_SEL_SHIFT = 2,
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ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT,
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ACLK_PERI_SEL_400M = 0,
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ACLK_PERI_SEL_200M,
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ACLK_PERI_SEL_100M,
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ACLK_PERI_SEL_24M,
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PCLK_PERI_SEL_SHIFT = 0,
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PCLK_PERI_SEL_MASK = 0x3 << PCLK_PERI_SEL_SHIFT,
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PCLK_PERI_SEL_100M = 0,
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PCLK_PERI_SEL_50M,
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PCLK_PERI_SEL_24M,
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/* CRU_PERI_CLK_SEL2_CON */
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CLK_I2C4_SEL_SHIFT = 0,
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CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
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/* CRU_PERI_CLK_SEL6_CON */
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CLK_PWM2_SEL_SHIFT = 11,
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CLK_PWM2_SEL_MASK = 0x3 << CLK_PWM2_SEL_SHIFT,
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CLK_PWM1_SEL_SHIFT = 9,
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CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM_SEL_100M = 0,
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CLK_PWM_SEL_50M,
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CLK_PWM_SEL_24M,
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CLK_PKA_CRYPTO_SEL_SHIFT = 7,
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CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
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CLK_CORE_CRYPTO_SEL_SHIFT = 5,
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CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
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CLK_CRYPTO_SEL_300M = 0,
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CLK_CRYPTO_SEL_200M,
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CLK_CRYPTO_SEL_100M,
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CLK_CRYPTO_SEL_24M,
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
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CLK_SPI1_SEL_SHIFT = 3,
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CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
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/* CRU_PERI_CLK_SEL7_CON */
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DCLK_DECOM_SEL_SHIFT = 14,
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DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT,
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DCLK_DECOM_SEL_400M = 0,
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DCLK_DECOM_SEL_200M,
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DCLK_DECOM_SEL_100M,
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DCLK_DECOM_SEL_24M,
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CLK_SFC_SEL_SHIFT = 12,
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CLK_SFC_SEL_MASK = 0x3 << CLK_SFC_SEL_SHIFT,
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CLK_SFC_SEL_500M = 0,
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CLK_SFC_SEL_300M,
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CLK_SFC_SEL_200M,
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CLK_SFC_SEL_24M,
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CLK_SFC_DIV_SHIFT = 7,
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CLK_SFC_DIV_MASK = 0x1f << CLK_SFC_DIV_SHIFT,
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CLK_EMMC_SEL_SHIFT = 6,
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CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT,
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CLK_MMC_SEL_400M = 0,
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CLK_MMC_SEL_24M,
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CLK_EMMC_DIV_SHIFT = 0,
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CLK_EMMC_DIV_MASK = 0x3f << CLK_EMMC_DIV_SHIFT,
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/* CRU_PERI_CLK_SEL9_CON */
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ACLK_BUS_SEL_SHIFT = 0,
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ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT,
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ACLK_BUS_SEL_300M = 0,
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ACLK_BUS_SEL_200M,
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ACLK_BUS_SEL_100M,
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ACLK_BUS_SEL_24M,
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/* CRU_PERI_CLK_SEL11_CON */
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CLK_PWM0_SEL_SHIFT = 0,
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CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
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/* CRU_VEPU_CLK_SEL0_CON */
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CLK_SPI0_SEL_SHIFT = 12,
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CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
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CLK_SPI0_SEL_200M = 0,
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CLK_SPI0_SEL_100M,
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CLK_SPI0_SEL_50M,
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CLK_SPI0_SEL_24M,
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/* CRU_CORE_CLK_SEL0_CON */
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CLK_CORE_DIV_SHIFT = 0,
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CLK_CORE_DIV_MASK = 0x1f << CLK_CORE_DIV_SHIFT,
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/* CRU_VI_CLK_SEL1_CON */
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CLK_SDMMC_SEL_SHIFT = 14,
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CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT,
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CLK_SDMMC_DIV_SHIFT = 8,
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CLK_SDMMC_DIV_MASK = 0x3f << CLK_SDMMC_DIV_SHIFT,
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/* CRU_VO_CLK_SEL1_CON */
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ACLK_VOP_SEL_SHIFT = 10,
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ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT,
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ACLK_VOP_SEL_300M = 0,
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ACLK_VOP_SEL_200M,
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ACLK_VOP_SEL_100M,
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ACLK_VOP_SEL_24M,
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/* CRU_VO_CLK_SEL3_CON */
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CLK_TSADC_TSEN_DIV_SHIFT = 5,
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CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
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CLK_TSADC_DIV_SHIFT = 0,
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CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
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};
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#endif
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