/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3308_H
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#define _ASM_ARCH_CRU_RK3308_H
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (816 * MHz)
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#define CORE_ACLK_HZ 408000000
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#define CORE_DBG_HZ 204000000
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#define BUS_ACLK_HZ 200000000
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#define BUS_HCLK_HZ 100000000
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#define BUS_PCLK_HZ 100000000
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#define PERI_ACLK_HZ 200000000
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#define PERI_HCLK_HZ 100000000
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#define PERI_PCLK_HZ 100000000
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#define AUDIO_HCLK_HZ 100000000
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#define AUDIO_PCLK_HZ 100000000
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#define RK3308_PLL_CON(x) ((x) * 0x4)
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#define RK3308_MODE_CON 0xa0
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/* RK3308 pll id */
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enum rk3308_pll_id {
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APLL,
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DPLL,
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VPLL0,
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VPLL1,
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PLL_COUNT,
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};
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struct rk3308_clk_info {
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unsigned long id;
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char *name;
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};
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3308_clk_priv {
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struct rk3308_cru *cru;
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ulong armclk_hz;
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ulong dpll_hz;
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ulong vpll0_hz;
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ulong vpll1_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3308_cru {
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struct rk3308_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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} pll[4];
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unsigned int reserved1[8];
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unsigned int mode;
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unsigned int misc;
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unsigned int reserved2[2];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int pll_lock;
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unsigned int reserved3[6];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[74];
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unsigned int reserved6[54];
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unsigned int clkgate_con[15];
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unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[10];
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unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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};
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_PDSEL_SHIFT = 15,
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PLL_PD1_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLLPD0_POWER_DOWN = 1,
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PLLPD0_NO_POWER_DOWN = 0,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* PLLCON2 */
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PLL_FOUT4PHASEPD_SHIFT = 27,
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PLL_FOUTVCOPD_SHIFT = 26,
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PLL_FOUTPOSTDIVPD_SHIFT = 25,
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PLL_DACPD_SHIFT = 24,
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PLL_FRAC_DIV = 0xffffff,
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/* CRU_MODE */
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PLLMUX_FROM_XIN24M = 0,
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PLLMUX_FROM_PLL,
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PLLMUX_FROM_RTC32K,
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USBPHY480M_MODE_SHIFT = 8,
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USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
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VPLL1_MODE_SHIFT = 6,
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VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
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VPLL0_MODE_SHIFT = 4,
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VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
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DPLL_MODE_SHIFT = 2,
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DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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/* CRU_CLK_SEL0_CON */
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CORE_ACLK_DIV_SHIFT = 12,
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CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 6,
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CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_VPLL0,
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CORE_CLK_PLL_SEL_VPLL1,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL2_CON */
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CLK_RTC32K_SEL_SHIFT = 8,
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CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT,
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CLK_RTC32K_IO = 0,
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CLK_RTC32K_PVTM,
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CLK_RTC32K_FRAC_DIV,
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CLK_RTC32K_DIV,
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/* CRU_CLK_SEL3_CON */
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CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16,
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CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL5_CON */
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BUS_PLL_SEL_SHIFT = 6,
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BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
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BUS_PLL_SEL_DPLL = 0,
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BUS_PLL_SEL_VPLL0,
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BUS_PLL_SEL_VPLL1,
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BUS_ACLK_DIV_SHIFT = 0,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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/* CRU_CLK_SEL6_CON */
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BUS_PCLK_DIV_SHIFT = 8,
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BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 0,
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BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
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/* CRU_CLK_SEL7_CON */
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CRYPTO_APK_SEL_SHIFT = 14,
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CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
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CRYPTO_PLL_SEL_DPLL = 0,
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CRYPTO_PLL_SEL_VPLL0,
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CRYPTO_PLL_SEL_VPLL1 = 0,
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CRYPTO_APK_DIV_SHIFT = 8,
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CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
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CRYPTO_PLL_SEL_SHIFT = 6,
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CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CRU_CLK_SEL8_CON */
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DCLK_VOP_SEL_SHIFT = 14,
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DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_DIVOUT = 0,
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DCLK_VOP_SEL_FRACOUT,
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DCLK_VOP_SEL_24M,
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DCLK_VOP_PLL_SEL_SHIFT = 10,
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DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
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DCLK_VOP_PLL_SEL_DPLL = 0,
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DCLK_VOP_PLL_SEL_VPLL0,
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DCLK_VOP_PLL_SEL_VPLL1,
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = 0xff,
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/* CRU_CLK_SEL25_CON */
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/* CRU_CLK_SEL26_CON */
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/* CRU_CLK_SEL27_CON */
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/* CRU_CLK_SEL28_CON */
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CLK_I2C_PLL_SEL_SHIFT = 14,
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CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
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CLK_I2C_PLL_SEL_DPLL = 0,
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CLK_I2C_PLL_SEL_VPLL0,
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CLK_I2C_PLL_SEL_24M,
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CLK_I2C_DIV_CON_SHIFT = 0,
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CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
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/* CRU_CLK_SEL29_CON */
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CLK_PWM_PLL_SEL_SHIFT = 14,
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CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
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CLK_PWM_PLL_SEL_DPLL = 0,
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CLK_PWM_PLL_SEL_VPLL0,
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CLK_PWM_PLL_SEL_24M,
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CLK_PWM_DIV_CON_SHIFT = 0,
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CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
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/* CRU_CLK_SEL30_CON */
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/* CRU_CLK_SEL31_CON */
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/* CRU_CLK_SEL32_CON */
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CLK_SPI_PLL_SEL_SHIFT = 14,
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CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
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CLK_SPI_PLL_SEL_DPLL = 0,
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CLK_SPI_PLL_SEL_VPLL0,
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CLK_SPI_PLL_SEL_24M,
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CLK_SPI_DIV_CON_SHIFT = 0,
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CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
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/* CRU_CLK_SEL34_CON */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
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/* CRU_CLK_SEL36_CON */
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PERI_PLL_SEL_SHIFT = 6,
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PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_DPLL = 0,
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PERI_PLL_VPLL0,
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PERI_PLL_VPLL1,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLK_SEL37_CON */
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PERI_PCLK_DIV_SHIFT = 8,
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PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
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PERI_HCLK_DIV_SHIFT = 0,
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PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
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/* CRU_CLKSEL41_CON */
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EMMC_CLK_SEL_SHIFT = 15,
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EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
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EMMC_CLK_SEL_EMMC = 0,
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EMMC_CLK_SEL_EMMC_DIV50,
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EMMC_PLL_SHIFT = 8,
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EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
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EMMC_SEL_DPLL = 0,
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EMMC_SEL_VPLL0,
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EMMC_SEL_VPLL1,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL42_CON */
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SCLK_SFC_SEL_SHIFT = 14,
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SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
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SCLK_SFC_SEL_DPLL = 0,
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SCLK_SFC_SEL_VPLL0,
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SCLK_SFC_SEL_VPLL1,
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SCLK_SFC_DIV_SHIFT = 0,
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SCLK_SFC_DIV_MASK = 0x7f << SCLK_SFC_DIV_SHIFT,
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/* CRU_CLKSEL43_CON */
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MAC_CLK_SPEED_SEL_SHIFT = 15,
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MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
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MAC_CLK_SPEED_SEL_10M = 0,
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MAC_CLK_SPEED_SEL_100M,
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MAC_CLK_SOURCE_SEL_SHIFT = 14,
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MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
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MAC_CLK_SOURCE_SEL_INTERNAL = 0,
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MAC_CLK_SOURCE_SEL_EXTERNAL,
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MAC_PLL_SHIFT = 6,
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MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
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MAC_SEL_DPLL = 0,
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MAC_SEL_VPLL0,
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MAC_SEL_VPLL1,
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MAC_DIV_SHIFT = 0,
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MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
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/* CRU_CLK_SEL45_CON */
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AUDIO_PCLK_DIV_SHIFT = 8,
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AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
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AUDIO_PLL_SEL_SHIFT = 6,
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AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
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AUDIO_PLL_VPLL0 = 0,
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AUDIO_PLL_VPLL1,
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AUDIO_PLL_24M,
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AUDIO_HCLK_DIV_SHIFT = 0,
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AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
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};
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check_member(rk3308_cru, emmc_con[1], 0x494);
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enum { /* DPLL_CON0, VPLL0_CON0, VPLL1_CON0 */
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POSTDIV1_SHIFT = 12,
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POSTDIV1_MASK = 0x7 << POSTDIV1_SHIFT,
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FBDIV_SHIFT = 0,
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FBDIV_MASK = 0xfff << FBDIV_SHIFT,
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/* DPLL_CON1, VPLL0_CON1, VPLL1_CON1 */
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PLLPD0_SHIFT = 13,
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PLLPD0_MASK = 1 << PLLPD0_SHIFT,
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DSMPD_SHIFT = 12,
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DSMPD_MASK = 1 << DSMPD_SHIFT,
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INTEGER_MODE = 1,
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FRACTIONAL_MODE = 0,
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PLL_LOCK_SHIFT = 10,
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PLL_LOCK_MASK = 0x1 << PLL_LOCK_SHIFT,
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POSTDIV2_SHIFT = 6,
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POSTDIV2_MASK = 0x7 << POSTDIV2_SHIFT,
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REFDIV_SHIFT = 0,
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REFDIV_MASK = 0x3f << REFDIV_SHIFT,
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/* VPLL0_CON2, VPLL1_CON2 */
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FRACDIV_SHIFT = 0,
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FRACDIV_MASK = 0xffffff << FRACDIV_SHIFT,
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/* CRU_MODE */
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VPLL1_CLK_SEL_SHIFT = 13,
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VPLL1_CLK_SEL_MASK = 0x1 << VPLL1_CLK_SEL_SHIFT,
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VPLL1_CLK_SEL_WITHOUT_LVL_SHIFT = 1,
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VPLL0_CLK_SEL_SHIFT = 12,
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VPLL0_CLK_SEL_MASK = 0x1 << VPLL0_CLK_SEL_SHIFT,
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VPLL0_CLK_SEL_WITHOUT_LVL_SHIFT = 1,
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DPLL_CLK_SEL_SHIFT = 11,
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DPLL_CLK_SEL_MASK = 0x1 << DPLL_CLK_SEL_SHIFT,
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DPLL_CLK_SEL_WITHOUT_LVL_SHIFT = 1,
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APLL_CLK_SEL_SHIFT = 10,
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APLL_CLK_SEL_MASK = 0x1 << APLL_CLK_SEL_SHIFT,
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APLL_CLK_SEL_WITHOUT_LVL_SHIFT = 1,
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VPLL1_WORK_MODE_SHIFT = 6,
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VPLL1_WORK_MODE_MASK = 0x3 << VPLL1_WORK_MODE_SHIFT,
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VPLL1_WORK_MODE_XIN_OSC0 = 0,
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VPLL1_WORK_MODE_PLL = 1,
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VPLL1_WORK_MODE_32K = 2,
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VPLL0_WORK_MODE_SHIFT = 4,
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VPLL0_WORK_MODE_MASK = 0x3 << VPLL0_WORK_MODE_SHIFT,
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VPLL0_WORK_MODE_XIN_OSC0 = 0,
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VPLL0_WORK_MODE_PLL = 1,
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VPLL0_WORK_MODE_32K = 2,
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DPLL_WORK_MODE_SHIFT = 2,
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DPLL_WORK_MODE_MASK = 0x3 << DPLL_WORK_MODE_SHIFT,
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DPLL_WORK_MODE_XIN_OSC0 = 0,
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DPLL_WORK_MODE_PLL = 1,
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DPLL_WORK_MODE_32K = 2,
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APLL_WORK_MODE_SHIFT = 0,
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APLL_WORK_MODE_MASK = 0x3 << APLL_WORK_MODE_SHIFT,
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APLL_WORK_MODE_XIN_OSC0 = 0,
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APLL_WORK_MODE_PLL = 1,
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/* GLB_RST_CON */
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WDT_GLB_SRST_CTRL_SHIFT = 1,
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WDT_GLB_SRST_CTRL = 1,
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TSADC_GLB_SRST_CTRL_SHIFT = 0,
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TSADC_GLB_SRST_CTRL = 1,
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/* CLKSEL_CON1 */
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DDRPHY4X_PLL_CLK_SEL_SHIFT = 6,
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DDRPHY4X_PLL_CLK_SEL_MASK = 0x3 << DDRPHY4X_PLL_CLK_SEL_SHIFT,
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DDRPHY4X_PLL_CLK_SEL_DPLL = 0,
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DDRPHY4X_DIV_CON_SIHFT = 0,
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DDRPHY4X_DIV_CON_MASK = 0x7 << DDRPHY4X_DIV_CON_SIHFT,
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DDRPHY4X_DIV_CON = 0,
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/* CLKSEL_CON5 */
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A_H_PCLK_BUS_PLL_SEL_SHIFT = 6,
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A_H_PCLK_BUS_PLL_SEL_MASK = 0x3 << A_H_PCLK_BUS_PLL_SEL_SHIFT,
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A_H_PCLK_BUS_PLL_SEL_DPLL = 0,
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A_H_PCLK_BUS_PLL_SEL_VPLL0 = 1,
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A_H_PCLK_BUS_PLL_SEL_VPLL1 = 2,
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ACLK_BUS_DIV_CON_SHIFT = 0,
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ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
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ACLK_BUS_DIV_CON_7 = 7,
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ACLK_BUS_DIV_CON_5 = 5,
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ACLK_BUS_DIV_CON_3 = 3,
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/* CLKSEL_CON6 */
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PCLK_BUS_DIV_CON_SHIFT = 8,
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PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT,
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PCLK_BUS_DIV_CON_31 = 31,
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PCLK_BUS_DIV_CON_25 = 25,
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PCLK_BUS_DIV_CON_15 = 15,
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HCLK_BUS_DIV_CON_SHIFT = 0,
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HCLK_BUS_DIV_CON_MASK = 0x1f << HCLK_BUS_DIV_CON_SHIFT,
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HCLK_BUS_DIV_CON_15 = 15,
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HCLK_BUS_DIV_CON_13 = 13,
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HCLK_BUS_DIV_CON_11 = 11,
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HCLK_BUS_DIV_CON_7 = 7,
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/* CLKSEL_CON7 */
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CLK_CRYPTO_APK_SEL_SHIFT = 14,
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CLK_CRYPTO_APK_SEL_MASK = 0x3 << CLK_CRYPTO_APK_SEL_SHIFT,
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CLK_CRYPTO_APK_SEL_DPLL = 0,
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CLK_CRYPTO_APK_DIV_SHIFT = 8,
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CLK_CRYPTO_APK_DIV_MASK = 0x1f << CLK_CRYPTO_APK_DIV_SHIFT,
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CLK_CRYPTO_APK_DIV_15 = 15,
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CLK_CRYPTO_APK_DIV_13 = 13,
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CLK_CRYPTO_APK_DIV_11 = 11,
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CLK_CRYPTO_APK_DIV_7 = 7,
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CLK_CRYPTO_PLL_SEL_SHIFT = 6,
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CLK_CRYPTO_PLL_SEL_MASK = 0x3 << CLK_CRYPTO_PLL_SEL_SHIFT,
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CLK_CRYPTO_PLL_SEL_DPLL = 0,
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CLK_CRYPTO_DIV_CON_SHIFT = 0,
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CLK_CRYPTO_DIV_CON_MASK = 0x1f << CLK_CRYPTO_DIV_CON_SHIFT,
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CLK_CRYPTO_DIV_CON_15 = 15,
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CLK_CRYPTO_DIV_CON_13 = 13,
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CLK_CRYPTO_DIV_CON_11 = 11,
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CLK_CRYPTO_DIV_CON_7 = 7,
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/* CLKSEL_CON8 */
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DCLK_VOP_SEL_DCLK_VOP = 0,
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DCLK_VOP_DIV_CON_SHIFT = 0,
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DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
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DCLK_VOP_DIV_CON_15 = 15,
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DCLK_VOP_DIV_CON_11 = 11,
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/* CLKSEL_CON10 */
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CLK_UART0_PLL_SEL_SHIFT = 13,
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CLK_UART0_PLL_SEL_MASK = 0x7 << CLK_UART0_PLL_SEL_SHIFT,
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CLK_UART0_PLL_SEL_XIN_OSC0 = 4,
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CLK_UART0_DIV_CON_SHIFT = 0,
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CLK_UART0_DIV_CON_MASK = 0x1f << CLK_UART0_DIV_CON_SHIFT,
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CLK_UART0_DIV_CON = 0,
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CLK_UART0_DIV_CON_15 = 15,
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/* CLKSEL_CON13 */
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CLK_UART1_PLL_SEL_SHIFT = 13,
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CLK_UART1_PLL_SEL_MASK = 0x7 << CLK_UART1_PLL_SEL_SHIFT,
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CLK_UART1_PLL_SEL_XIN_OSC0 = 4,
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CLK_UART1_DIV_CON_SHIFT = 0,
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CLK_UART1_DIV_CON_MASK = 0x1f << CLK_UART1_DIV_CON_SHIFT,
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CLK_UART1_DIV_CON = 0,
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CLK_UART1_DIV_CON_15 = 15,
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/* CLKSEL_CON16 */
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CLK_UART2_PLL_SEL_SHIFT = 13,
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CLK_UART2_PLL_SEL_MASK = 0x7 << CLK_UART2_PLL_SEL_SHIFT,
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CLK_UART2_PLL_SEL_XIN_OSC0 = 4,
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CLK_UART2_DIV_CON_SHIFT = 0,
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CLK_UART2_DIV_CON_MASK = 0x1f << CLK_UART2_DIV_CON_SHIFT,
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CLK_UART2_DIV_CON = 0,
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CLK_UART2_DIV_CON_15 = 15,
|
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/* CLKSEL_CON19 */
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CLK_UART3_PLL_SEL_SHIFT = 13,
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CLK_UART3_PLL_SEL_MASK = 0x7 << CLK_UART3_PLL_SEL_SHIFT,
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CLK_UART3_PLL_SEL_XIN_OSC0 = 4,
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CLK_UART3_DIV_CON_SHIFT = 0,
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CLK_UART3_DIV_CON_MASK = 0x1f << CLK_UART3_DIV_CON_SHIFT,
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CLK_UART3_DIV_CON = 0,
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CLK_UART3_DIV_CON_15 = 15,
|
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/* CLKSEL_CON22 */
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CLK_UART4_PLL_SEL_SHIFT = 13,
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CLK_UART4_PLL_SEL_MASK = 0x7 << CLK_UART4_PLL_SEL_SHIFT,
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CLK_UART4_PLL_SEL_XIN_OSC0 = 4,
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CLK_UART4_DIV_CON_SHIFT = 0,
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CLK_UART4_DIV_CON_MASK = 0x1f << CLK_UART4_DIV_CON_SHIFT,
|
CLK_UART4_DIV_CON = 0,
|
CLK_UART4_DIV_CON_15 = 15,
|
|
/* CLKSEL_CON25 */
|
CLK_I2C0_PLL_SEL_SHIFT = 14,
|
CLK_I2C0_PLL_SEL_MASK = 0x3 << CLK_I2C0_PLL_SEL_SHIFT,
|
CLK_I2C0_PLL_SEL_DPLL = 0,
|
CLK_I2C0_DIV_CON_SHIFT = 0,
|
CLK_I2C0_DIV_CON_MASK = 0x7f << CLK_I2C0_DIV_CON_SHIFT,
|
CLK_I2C0_DIV_CON_7 = 7,
|
CLK_I2C0_DIV_CON_5 = 5,
|
CLK_I2C0_DIV_CON_3 = 3,
|
|
/* CLKSEL_CON26 */
|
CLK_I2C1_PLL_SEL_SHIFT = 14,
|
CLK_I2C1_PLL_SEL_MASK = 0x3 << CLK_I2C1_PLL_SEL_SHIFT,
|
CLK_I2C1_PLL_SEL_DPLL = 0,
|
CLK_I2C1_DIV_CON_SHIFT = 0,
|
CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT,
|
CLK_I2C1_DIV_CON_7 = 7,
|
CLK_I2C1_DIV_CON_5 = 5,
|
CLK_I2C1_DIV_CON_3 = 3,
|
|
/* CLKSEL_CON27 */
|
CLK_I2C2_PLL_SEL_SHIFT = 14,
|
CLK_I2C2_PLL_SEL_MASK = 0x3 << CLK_I2C2_PLL_SEL_SHIFT,
|
CLK_I2C2_PLL_SEL_DPLL = 0,
|
CLK_I2C2_DIV_CON_SHIFT = 0,
|
CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT,
|
CLK_I2C2_DIV_CON_7 = 7,
|
CLK_I2C2_DIV_CON_5 = 5,
|
CLK_I2C2_DIV_CON_3 = 3,
|
|
/* CLKSEL_CON28 */
|
CLK_I2C3_PLL_SEL_SHIFT = 14,
|
CLK_I2C3_PLL_SEL_MASK = 0x3 << CLK_I2C3_PLL_SEL_SHIFT,
|
CLK_I2C3_PLL_SEL_DPLL = 0,
|
CLK_I2C3_DIV_CON_SHIFT = 0,
|
CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT,
|
CLK_I2C3_DIV_CON_7 = 7,
|
CLK_I2C3_DIV_CON_5 = 5,
|
CLK_I2C3_DIV_CON_3 = 3,
|
|
/* CLKSEL_CON29 */
|
CLK_PWM_DIV_CON_15 = 15,
|
CLK_PWM_DIV_CON_11 = 11,
|
CLK_PWM_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON30 */
|
CLK_SPI0_PLL_SEL_SHIFT = 14,
|
CLK_SPI0_PLL_SEL_MASK = 0x3 << CLK_SPI0_PLL_SEL_SHIFT,
|
CLK_SPI0_PLL_SEL_DPLL = 0,
|
CLK_SPI0_DIV_CON_SHIFT = 0,
|
CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT,
|
CLK_SPI0_DIV_CON_15 = 15,
|
CLK_SPI0_DIV_CON_11 = 11,
|
CLK_SPI0_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON31 */
|
CLK_SPI1_PLL_SEL_SHIFT = 14,
|
CLK_SPI1_PLL_SEL_MASK = 0x3 << CLK_SPI1_PLL_SEL_SHIFT,
|
CLK_SPI1_PLL_SEL_DPLL = 0,
|
CLK_SPI1_DIV_CON_SHIFT = 0,
|
CLK_SPI1_DIV_CON_MASK = 0x7f << CLK_SPI1_DIV_CON_SHIFT,
|
CLK_SPI1_DIV_CON_15 = 15,
|
CLK_SPI1_DIV_CON_11 = 11,
|
CLK_SPI1_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON32 */
|
CLK_SPI2_PLL_SEL_SHIFT = 14,
|
CLK_SPI2_PLL_SEL_MASK = 0x3 << CLK_SPI2_PLL_SEL_SHIFT,
|
CLK_SPI2_PLL_SEL_DPLL = 0,
|
CLK_SPI2_DIV_CON_SHIFT = 0,
|
CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT,
|
CLK_SPI2_DIV_CON_15 = 15,
|
CLK_SPI2_DIV_CON_11 = 11,
|
CLK_SPI2_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON36 */
|
A_H_P_PERI_PLL_SEL_SHIFT = 6,
|
A_H_P_PERI_PLL_SEL_MASK = 0x3 << A_H_P_PERI_PLL_SEL_SHIFT,
|
A_H_P_PERI_PLL_SEL_DPLL = 0,
|
ACLK_PERI_DIV_CON_SHIFT = 0,
|
ACLK_PERI_DIV_CON_MASK = 0x1f << ACLK_PERI_DIV_CON_SHIFT,
|
ACLK_PERI_DIV_CON_7 = 7,
|
ACLK_PERI_DIV_CON_5 = 5,
|
ACLK_PERI_DIV_CON_3 = 3,
|
|
/* CLKSEL_CON37 */
|
PCLK_PERI_DIV_CON_SHIFT = 8,
|
PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT,
|
PCLK_PERI_DIV_CON_31 = 31,
|
PCLK_PERI_DIV_CON_27 = 27,
|
PCLK_PERI_DIV_CON_23 = 23,
|
PCLK_PERI_DIV_CON_15 = 15,
|
HCLK_PERI_DIV_CON_SHIFT = 0,
|
HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT,
|
HCLK_PERI_DIV_CON_15 = 15,
|
HCLK_PERI_DIV_CON_13 = 13,
|
HCLK_PERI_DIV_CON_11 = 11,
|
HCLK_PERI_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON38 */
|
CLK_NANDC_SEL50_SHIFT = 15,
|
CLK_NANDC_SEL50_MASK = 0x1 << CLK_NANDC_SEL50_SHIFT,
|
CLK_NANDC_SEL50_EVEN = 0,
|
CLK_NANDC_SEL50_ALWAYS = 1,
|
CLK_NANDC_PLL_SEL_SHIFT = 6,
|
CLK_NANDC_PLL_SEL_MASK = 0x3 << CLK_NANDC_PLL_SEL_SHIFT,
|
CLK_NANDC_PLL_SEL_DPLL = 0,
|
CLK_NANDC_DIV_CON_SHIFT = 0,
|
CLK_NANDC_DIV_CON_MASK = 0x1f << CLK_NANDC_DIV_CON_SHIFT,
|
CLK_NANDC_DIV_CON_15 = 15,
|
CLK_NANDC_DIV_CON_13 = 13,
|
CLK_NANDC_DIV_CON_11 = 11,
|
CLK_NANDC_DIV_CON_7 = 7,
|
|
/* CLKSEL_CON39 */
|
CLK_SDMMC_SEL50_SHIFT = 15,
|
CLK_SDMMC_SEL50_MASK = 0x1 << CLK_SDMMC_SEL50_SHIFT,
|
CLK_SDMMC_SEL50_EVEN = 0,
|
CLK_SDMMC_SEL50_ALWAYS = 1,
|
CLK_SDMMC_PLL_SEL_SHIFT = 8,
|
CLK_SDMMC_PLL_SEL_MASK = 0x3 << CLK_SDMMC_PLL_SEL_SHIFT,
|
CLK_SDMMC_PLL_SEL_DPLL = 0,
|
CLK_SDMMC_DIV_CON_SHIFT = 0,
|
CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
|
CLK_SDMMC_DIV_CON_31 = 31,
|
CLK_SDMMC_DIV_CON_27 = 27,
|
CLK_SDMMC_DIV_CON_23 = 23,
|
CLK_SDMMC_DIV_CON_15 = 15,
|
|
/* CLKSEL_CON40 */
|
CLK_SDIO_SEL50_SHIFT = 15,
|
CLK_SDIO_SEL50_MASK = 0x1 << CLK_SDIO_SEL50_SHIFT,
|
CLK_SDIO_SEL50_EVEN = 0,
|
CLK_SDIO_SEL50_ALWAYS = 1,
|
CLK_SDIO_PLL_SEL_SHIFT = 8,
|
CLK_SDIO_PLL_SEL_MASK = 0x3 << CLK_SDIO_PLL_SEL_SHIFT,
|
CLK_SDIO_PLL_SEL_DPLL = 0,
|
CLK_SDIO_DIV_CON_SHIFT = 0,
|
CLK_SDIO_DIV_CON_MASK = 0xff << CLK_SDIO_DIV_CON_SHIFT,
|
CLK_SDIO_DIV_CON_4 = 4,
|
CLK_SDIO_DIV_CON_3 = 3,
|
CLK_SDIO_DIV_CON_2 = 2,
|
|
/* CLKSEL_CON41 */
|
CLK_EMMC_SEL50_SHIFT = 15,
|
CLK_EMMC_SEL50_MASK = 0x1 << CLK_EMMC_SEL50_SHIFT,
|
CLK_EMMC_SEL50_EVEN = 0,
|
CLK_EMMC_SEL50_ALWAYS = 1,
|
CLK_EMMC_PLL_SEL_SHIFT = 8,
|
CLK_EMMC_PLL_SEL_MASK = 0x3 << CLK_EMMC_PLL_SEL_SHIFT,
|
CLK_EMMC_PLL_SEL_DPLL = 0,
|
CLK_EMMC_DIV_CON_SHIFT = 0,
|
CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
|
CLK_EMMC_DIV_CON_31 = 31,
|
CLK_EMMC_DIV_CON_27 = 27,
|
CLK_EMMC_DIV_CON_23 = 23,
|
CLK_EMMC_DIV_CON_15 = 15,
|
|
/* CLKSEL_CON42 */
|
CLK_SFC_PLL_SEL_SHIFT = 14,
|
CLK_SFC_PLL_SEL_MASK = 0x3 << CLK_SFC_PLL_SEL_SHIFT,
|
CLK_SFC_PLL_SEL_DPLL = 0,
|
CLK_SFC_DIV_CON_SHIFT = 0,
|
CLK_SFC_DIV_CON_MASK = 0x7f << CLK_SFC_DIV_CON_SHIFT,
|
CLK_SFC_DIV_CON_65 = 65,
|
CLK_SFC_DIV_CON_53 = 53,
|
CLK_SFC_DIV_CON_49 = 49,
|
CLK_SFC_DIV_CON_31 = 31,
|
|
/* CLKSEL_CON43 */
|
RMII_CLK_SEL_SHIFT = 15,
|
RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT,
|
RMII_CLK_SEL_100M = 1,
|
RMII_CLK_SEL_10M = 0,
|
RMII_EXTCLKSRC_SEL_SHIFT = 14,
|
RMII_EXTCLKSRC_SEL_MASK = 0x1 << RMII_EXTCLKSRC_SEL_SHIFT,
|
RMII_EXTCLKSRC_SEL_CLK_MAC = 0,
|
CLK_MAC_PLL_SEL_SHIFT = 6,
|
CLK_MAC_PLL_SEL_MASK = 0x3 << CLK_MAC_PLL_SEL_SHIFT,
|
CLK_MAC_PLL_SEL_DPLL = 0,
|
CLK_MAC_DIV_CON_SHIFT = 0,
|
CLK_MAC_DIV_CON_MASK = 0x1f << CLK_MAC_DIV_CON_SHIFT,
|
CLK_MAC_DIV_CON_31 = 31,
|
CLK_MAC_DIV_CON_23 = 23,
|
CLK_MAC_DIV_CON_25 = 25,
|
|
/* CLKSEL_CON44 */
|
CLK_WIFI_SEL_SHIFT = 7,
|
CLK_WIFI_SEL_MASK = 0x1 << CLK_WIFI_SEL_SHIFT,
|
CLK_WIFI_SEL_CLK_WIFI = 1,
|
CLK_WIFI_PLL_SEL_SHIFT = 6,
|
CLK_WIFI_PLL_SEL_MASK = 0x1 << CLK_WIFI_PLL_SEL_SHIFT,
|
CLK_WIFI_PLL_SEL_DPLL = 0,
|
CLK_WIFI_DIV_CON_SHIFT = 0,
|
CLK_WIFI_DIV_CON_MASK = 0x3f << CLK_WIFI_DIV_CON_SHIFT,
|
CLK_WIFI_DIV_CON_39 = 39,
|
CLK_WIFI_DIV_CON_29 = 29,
|
CLK_WIFI_DIV_CON_49 = 49,
|
CLK_WIFI_DIV_CON_19 = 19,
|
|
/* CLKSEL_CON45 */
|
PCLK_AUDIO_DIV_CON_SHIFT = 8,
|
PCLK_AUDIO_DIV_CON_MASK = 0x1f << PCLK_AUDIO_DIV_CON_SHIFT,
|
PCLK_AUDIO_DIV_CON_9 = 9,
|
H_PCLK_AUDIO_PLL_SEL_SHIFT = 6,
|
H_PCLK_AUDIO_PLL_SEL_MASK = 0x3 << H_PCLK_AUDIO_PLL_SEL_SHIFT,
|
H_PCLK_AUDIO_PLL_SEL_VPLL0 = 0,
|
HCLK_AUDIO_DIV_CON_SHIFT = 0,
|
HCLK_AUDIO_DIV_CON_MASK = 0x1f << HCLK_AUDIO_DIV_CON_SHIFT,
|
HCLK_AUDIO_DIV_CON_9 = 9,
|
|
/* CLKSEL_CON46 */
|
CLK_PDM_SEL_SHIFT = 15,
|
CLK_PDM_SEL_MASK = 0x1 << CLK_PDM_SEL_SHIFT,
|
CLK_PDM_SEL_CLK_PDM = 0,
|
CLK_PDM_PLL_SEL_SHIFT = 8,
|
CLK_PDM_PLL_SEL_MASK = 0x3 << CLK_PDM_PLL_SEL_SHIFT,
|
CLK_PDM_PLL_SEL_VPLL0 = 0,
|
CLK_PDM_DIV_CON_SHIFT = 0,
|
CLK_PDM_DIV_CON_MASK = 0x7f << CLK_PDM_DIV_CON_SHIFT,
|
CLK_PDM_DIV_CON_15 = 15,
|
|
/* CLKSEL_CON48 */
|
CLK_SPDIFTX_DIV_CON_SHIFT = 0,
|
CLK_SPDIFTX_DIV_CON_MASK = 0x7f << CLK_SPDIFTX_DIV_CON_SHIFT,
|
CLK_SPDIFTX_DIV_CON_15 = 15,
|
|
/* CLKSEL_CON52,CLKSEL_CON56,CLKSEL_CON60,CLKSEL_CON64 */
|
I2S_8CH_OUT_SEL_SHIFT = 15,
|
I2S_8CH_OUT_SEL_MASK = 0x1 << I2S_8CH_OUT_SEL_SHIFT,
|
I2S_8CH_OUT_SEL_TX_RX = 0,
|
I2S_8CH_TX_RX_SEL_SHIFT = 12,
|
I2S_8CH_TX_RX_SEL_MASK = 0x1 << I2S_8CH_TX_RX_SEL_SHIFT,
|
I2S_8CH_TX_RX_SEL_TX = 0,
|
I2S_8CH_TX_SEL_SHIFT = 10,
|
I2S_8CH_TX_SEL_MASK = 0x3 << I2S_8CH_TX_SEL_SHIFT,
|
I2S_8CH_TX_SEL_TX = 0,
|
I2S_8CH_TX_PLL_SEL_SHIFT = 8,
|
I2S_8CH_TX_PLL_SEL_MASK = 0x3 << I2S_8CH_TX_PLL_SEL_SHIFT,
|
I2S_8CH_TX_PLL_SEL_VPLL1 = 1,
|
I2S_8CH_TX_DIV_CON_SHIFT = 0,
|
I2S_8CH_TX_DIV_CON_MASK = 0x7f << I2S_8CH_TX_DIV_CON_SHIFT,
|
I2S_8CH_TX_DIV_CON_17 = 17,
|
|
/* CLKSEL_CON54,CLKSEL_CON58,CLKSEL_CON62,CLKSEL_CON66 */
|
I2S_8CH_RX_TX_SEL_SHIFT = 12,
|
I2S_8CH_RX_TX_SEL_MASK = 0x1 << I2S_8CH_RX_TX_SEL_SHIFT,
|
I2S_8CH_RX_TX_SEL_RX = 0,
|
I2S_8CH_RX_SEL_SHIFT = 10,
|
I2S_8CH_RX_SEL_MASK = 0x3 << I2S_8CH_RX_SEL_SHIFT,
|
I2S_8CH_RX_SEL_RX = 0,
|
I2S_8CH_RX_PLL_SEL_SHIFT = 8,
|
I2S_8CH_RX_PLL_SEL_MASK = 0x3 << I2S_8CH_RX_PLL_SEL_SHIFT,
|
I2S_8CH_RX_PLL_SEL_VPLL0 = 0,
|
I2S_8CH_RX_DIV_CON_SHIFT = 0,
|
I2S_8CH_RX_DIV_CON_MASK = 0x7f << I2S_8CH_RX_DIV_CON_SHIFT,
|
I2S_8CH_RX_DIV_CON_19 = 19,
|
|
/* SOFTRST_CON1 */
|
PRESETN_DDRPHY_REQ_SHIFT = 14,
|
PRESETN_DDRPHY_REQ_MASK = 0x1 << PRESETN_DDRPHY_REQ_SHIFT,
|
PRESETN_DDRPHY_REQ_EN = 1,
|
PRESETN_DDRPHY_REQ_DIS = 0,
|
|
RESETN_DDRPHYDIV_REQ_SHIFT = 13,
|
RESETN_DDRPHYDIV_REQ_MASK = 0x1 << RESETN_DDRPHYDIV_REQ_SHIFT,
|
RESETN_DDRPHYDIV_REQ_EN = 1,
|
RESETN_DDRPHYDIV_REQ_DIS = 0,
|
|
RESETN_DDRPHY_REQ_SHIFT = 12,
|
RESETN_DDRPHY_REQ_MASK = 0x1 << RESETN_DDRPHY_REQ_SHIFT,
|
RESETN_DDRPHY_REQ_EN = 1,
|
RESETN_DDRPHY_REQ_DIS = 0,
|
|
PRESETN_DDRUPCTL_REQ_SHIFT = 6,
|
PRESETN_DDRUPCTL_REQ_MASK = 0x1 << PRESETN_DDRUPCTL_REQ_SHIFT,
|
PRESETN_DDRUPCTL_REQ_EN = 1,
|
PRESETN_DDRUPCTL_REQ_DIS = 0,
|
|
RESETN_DDRUPCTL_REQ_SHIFT = 4,
|
RESETN_DDRUPCTL_REQ_MASK = 0x1 << RESETN_DDRUPCTL_REQ_SHIFT,
|
RESETN_DDRUPCTL_REQ_EN = 1,
|
RESETN_DDRUPCTL_REQ_DIS = 0,
|
|
/* CLKGATE_CON4 */
|
CLK_PMU_PVTM_CLK_EN_SHIFT = 4,
|
CLK_PMU_PVTM_CLK_EN_MASK = 0x1 << CLK_PMU_PVTM_CLK_EN_SHIFT,
|
CLK_PMU_PVTM_CLK_EN = 0,
|
|
/* SOFTRST_CON5 */
|
RESETN_PMU_PVTM_REQ_SHIFT = 1,
|
RESETN_PMU_PVTM_REQ_MASK = 0x1 << RESETN_PMU_PVTM_REQ_SHIFT,
|
RESETN_PMU_PVTM_REQ_ACT = 1,
|
RESETN_PMU_PVTM_REQ_DIS = 0,
|
};
|
|
#endif
|
