/*
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* am35x_def.h - TI's AM35x specific definitions.
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*
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* Based on arch/arm/include/asm/arch-omap3/cpu.h
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*
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* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
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*
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* Copyright (c) 2010 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _AM35X_DEF_H_
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#define _AM35X_DEF_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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/* LVL_INTR_CLEAR bits */
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#define USBOTGSS_INT_CLR (1 << 4)
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/* IP_SW_RESET bits */
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#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
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#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
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/* DEVCONF2 bits */
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#define CONF2_PHY_GPIOMODE (1 << 23)
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#define CONF2_OTGMODE (3 << 14)
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#define CONF2_NO_OVERRIDE (0 << 14)
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#define CONF2_FORCE_HOST (1 << 14)
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#define CONF2_FORCE_DEVICE (2 << 14)
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#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
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#define CONF2_SESENDEN (1 << 13)
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#define CONF2_VBDTCTEN (1 << 12)
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#define CONF2_REFFREQ_24MHZ (2 << 8)
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#define CONF2_REFFREQ_26MHZ (7 << 8)
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#define CONF2_REFFREQ_13MHZ (6 << 8)
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#define CONF2_REFFREQ (0xf << 8)
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#define CONF2_PHYCLKGD (1 << 7)
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#define CONF2_VBUSSENSE (1 << 6)
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#define CONF2_PHY_PLLON (1 << 5)
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#define CONF2_RESET (1 << 4)
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#define CONF2_PHYPWRDN (1 << 3)
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#define CONF2_OTGPWRDN (1 << 2)
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#define CONF2_DATPOL (1 << 1)
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/* General register mappings of system control module */
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#define AM35X_SCM_GEN_BASE 0x48002270
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struct am35x_scm_general {
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u32 res1[0xC4]; /* 0x000 - 0x30C */
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u32 devconf2; /* 0x310 */
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u32 devconf3; /* 0x314 */
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u32 res2[0x2]; /* 0x318 - 0x31C */
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u32 cba_priority; /* 0x320 */
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u32 lvl_intr_clr; /* 0x324 */
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u32 ip_sw_reset; /* 0x328 */
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u32 ipss_clk_ctrl; /* 0x32C */
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};
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#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
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#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
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#endif /*__ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#endif /* _AM35X_DEF_H_ */
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