/*
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* Copyright 2014, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV7_LS102XA_CONFIG_
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#define _ASM_ARMV7_LS102XA_CONFIG_
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#define OCRAM_BASE_ADDR 0x10000000
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#define OCRAM_SIZE 0x00010000
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#define OCRAM_BASE_S_ADDR 0x10010000
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#define OCRAM_S_SIZE 0x00010000
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_DCSRBAR 0x20000000
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#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
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#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
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#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
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#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
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#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
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#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
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#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
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#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
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#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
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#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
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#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
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#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
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#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
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#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
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#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
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#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
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#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
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#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
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#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
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#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
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#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
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#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
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#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
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#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
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#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
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#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
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#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
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#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
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#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
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#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
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/*
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* TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
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* So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
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*/
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#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
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CONFIG_SYS_PCIE1_VIRT_ADDR)
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#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
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CONFIG_SYS_PCIE2_VIRT_ADDR)
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/* SATA */
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#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#ifdef CONFIG_DDR_SPD
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
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#endif
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#define CONFIG_SYS_FSL_IFC_BE
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#define CONFIG_SYS_FSL_ESDHC_BE
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#define CONFIG_SYS_FSL_WDOG_BE
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#define CONFIG_SYS_FSL_DSPI_BE
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#define CONFIG_SYS_FSL_QSPI_BE
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#define CONFIG_SYS_FSL_DCU_BE
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#define CONFIG_SYS_FSL_SEC_MON_LE
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#define CONFIG_SYS_FSL_SFP_VER_3_2
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#define CONFIG_SYS_FSL_SFP_BE
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#define CONFIG_SYS_FSL_SRK_LE
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#define DCU_LAYER_MAX_NUM 16
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#ifdef CONFIG_ARCH_LS1021A
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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#define FSL_IFC_COMPAT "fsl,ifc"
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#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
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#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
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#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
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