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| /*
| * Xilinx ZED board DTS
| *
| * Copyright (C) 2011 - 2015 Xilinx
| * Copyright (C) 2012 National Instruments Corp.
| *
| * SPDX-License-Identifier: GPL-2.0+
| */
| /dts-v1/;
| #include "zynq-7000.dtsi"
|
| / {
| model = "Zynq Zed Development Board";
| compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
|
| aliases {
| ethernet0 = &gem0;
| serial0 = &uart1;
| spi0 = &qspi;
| mmc0 = &sdhci0;
| };
|
| memory@0 {
| device_type = "memory";
| reg = <0x0 0x20000000>;
| };
|
| chosen {
| bootargs = "";
| stdout-path = "serial0:115200n8";
| };
|
| usb_phy0: phy0 {
| compatible = "usb-nop-xceiv";
| #phy-cells = <0>;
| };
| };
|
| &clkc {
| ps-clk-frequency = <33333333>;
| };
|
| &gem0 {
| status = "okay";
| phy-mode = "rgmii-id";
| phy-handle = <ðernet_phy>;
|
| ethernet_phy: ethernet-phy@0 {
| reg = <0>;
| };
| };
|
| &qspi {
| u-boot,dm-pre-reloc;
| status = "okay";
| };
|
| &sdhci0 {
| u-boot,dm-pre-reloc;
| status = "okay";
| };
|
| &uart1 {
| u-boot,dm-pre-reloc;
| status = "okay";
| };
|
| &usb0 {
| status = "okay";
| dr_mode = "host";
| usb-phy = <&usb_phy0>;
| };
|
|
