/*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rk3568.dtsi"
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#include "rk3568-u-boot.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Rockchip RK3568 Evaluation Board";
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compatible = "rockchip,rk3568-evb", "rockchip,rk3568";
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adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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u-boot,dm-spl;
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status = "okay";
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volumeup-key {
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u-boot,dm-spl;
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linux,code = <KEY_VOLUMEUP>;
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label = "volume up";
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press-threshold-microvolt = <9>;
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};
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};
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};
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&gmac0 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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phy-handle = <&rgmii_phy0>;
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status = "disabled";
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};
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&gmac1 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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tx_delay = <0x4f>;
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rx_delay = <0x26>;
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phy-handle = <&rgmii_phy1>;
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status = "disabled";
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};
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&mdio0 {
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rgmii_phy0: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&mdio1 {
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rgmii_phy1: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&crypto {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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