/*
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* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/timer.h>
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#include <asm/io.h>
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static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
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static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static void lpc32xx_timer_clock(u32 bit, int enable)
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{
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if (enable)
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setbits_le32(&clk->timclk_ctrl1, bit);
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else
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clrbits_le32(&clk->timclk_ctrl1, bit);
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}
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static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
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{
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writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
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writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
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writel(0, &timer->tc);
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writel(0, &timer->pr);
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/* Count mode is every rising PCLK edge */
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writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
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/* Set prescale counter value */
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writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
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}
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static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
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{
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if (enable)
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writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
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else
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writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
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}
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int timer_init(void)
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{
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lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
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lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
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lpc32xx_timer_count(timer0, 1);
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return 0;
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}
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ulong get_timer(ulong base)
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{
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return readl(&timer0->tc) - base;
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}
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void __udelay(unsigned long usec)
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{
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lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
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lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
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lpc32xx_timer_count(timer1, 1);
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while (readl(&timer1->tc) < usec)
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/* NOP */;
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lpc32xx_timer_count(timer1, 0);
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lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
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}
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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