/*
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* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/ {
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axs10x_mb@e0000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xe0000000 0x10000000>;
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u-boot,dm-pre-reloc;
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clocks {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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uartclk: uartclk {
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compatible = "fixed-clock";
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clock-frequency = <33333333>;
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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ethernet@18000 {
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#interrupt-cells = <1>;
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compatible = "altr,socfpga-stmmac";
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reg = < 0x18000 0x2000 >;
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interrupts = < 25 >;
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interrupt-names = "macirq";
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phy-mode = "gmii";
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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};
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ehci@0x40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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interrupts = < 8 >;
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};
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ohci@0x60000 {
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compatible = "generic-ohci";
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reg = < 0x60000 0x100 >;
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interrupts = < 8 >;
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};
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uart0: serial0@22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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clocks = <&uartclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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};
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};
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