/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver
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*
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* Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
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*
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* Partly based on code copyright/by:
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*
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* Copyright (c) 2011,2012 Toradex Inc.
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*/
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#ifndef __TEGRA20_AC97_H__
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#define __TEGRA20_AC97_H__
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#include "tegra_pcm.h"
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#define TEGRA20_AC97_CTRL 0x00
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#define TEGRA20_AC97_CMD 0x04
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#define TEGRA20_AC97_STATUS1 0x08
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/* ... */
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#define TEGRA20_AC97_FIFO1_SCR 0x1c
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/* ... */
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#define TEGRA20_AC97_FIFO_TX1 0x40
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#define TEGRA20_AC97_FIFO_RX1 0x80
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/* TEGRA20_AC97_CTRL */
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#define TEGRA20_AC97_CTRL_STM2_EN (1 << 16)
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#define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11)
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#define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10)
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#define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9)
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#define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8)
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#define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7)
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#define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6)
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#define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5)
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#define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4)
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#define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3)
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#define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2)
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#define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1)
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#define TEGRA20_AC97_CTRL_STM_EN (1 << 0)
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/* TEGRA20_AC97_CMD */
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#define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24
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#define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT)
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#define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8
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#define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT)
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#define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2
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#define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT)
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#define TEGRA20_AC97_CMD_BUSY (1 << 0)
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/* TEGRA20_AC97_STATUS1 */
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#define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24
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#define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT)
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#define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8
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#define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT)
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#define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2)
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#define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1)
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#define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0)
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/* TEGRA20_AC97_FIFO1_SCR */
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#define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27
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#define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT)
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#define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22
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#define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT)
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#define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19)
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#define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18)
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#define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17)
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#define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16)
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#define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15)
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#define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14)
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#define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13)
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#define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12)
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#define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11)
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#define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10)
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#define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9)
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#define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8)
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struct tegra20_ac97 {
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struct clk *clk_ac97;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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int reset_gpio;
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int sync_gpio;
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};
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#endif /* __TEGRA20_AC97_H__ */
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