/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra186_dspk.h - Definitions for Tegra186 DSPK driver
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA186_DSPK_H__
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#define __TEGRA186_DSPK_H__
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/* Register offsets from DSPK BASE */
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#define TEGRA186_DSPK_RX_STATUS 0x0c
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#define TEGRA186_DSPK_RX_INT_STATUS 0x10
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#define TEGRA186_DSPK_RX_INT_MASK 0x14
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#define TEGRA186_DSPK_RX_INT_SET 0x18
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#define TEGRA186_DSPK_RX_INT_CLEAR 0x1c
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#define TEGRA186_DSPK_RX_CIF_CTRL 0x20
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#define TEGRA186_DSPK_ENABLE 0x40
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#define TEGRA186_DSPK_SOFT_RESET 0x44
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#define TEGRA186_DSPK_CG 0x48
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#define TEGRA186_DSPK_STATUS 0x4c
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#define TEGRA186_DSPK_INT_STATUS 0x50
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#define TEGRA186_DSPK_CORE_CTRL 0x60
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#define TEGRA186_DSPK_CODEC_CTRL 0x64
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/* DSPK CORE CONTROL fields */
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#define CH_SEL_SHIFT 8
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#define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT)
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#define DSPK_OSR_SHIFT 4
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#define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT)
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#define LRSEL_POL_SHIFT 0
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#define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
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#define TEGRA186_DSPK_RX_FIFO_DEPTH 64
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#define DSPK_OSR_FACTOR 32
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/* DSPK interface clock ratio */
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#define DSPK_CLK_RATIO 4
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enum tegra_dspk_osr {
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DSPK_OSR_32,
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DSPK_OSR_64,
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DSPK_OSR_128,
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DSPK_OSR_256,
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};
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enum tegra_dspk_ch_sel {
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DSPK_CH_SELECT_LEFT,
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DSPK_CH_SELECT_RIGHT,
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DSPK_CH_SELECT_STEREO,
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};
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enum tegra_dspk_lrsel {
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DSPK_LRSEL_LEFT,
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DSPK_LRSEL_RIGHT,
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};
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struct tegra186_dspk {
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unsigned int rx_fifo_th;
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unsigned int osr_val;
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unsigned int lrsel;
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unsigned int ch_sel;
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unsigned int mono_to_stereo;
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unsigned int stereo_to_mono;
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struct clk *clk_dspk;
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struct regmap *regmap;
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};
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#endif
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