/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2019 Intel Corporation. All rights reserved.
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*
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* Author: Keyon Jie <yang.jie@linux.intel.com>
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*/
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#ifndef __SOF_INTEL_HDA_IPC_H
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#define __SOF_INTEL_HDA_IPC_H
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/*
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* Primary register, mapped to
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* - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
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* - DIPCT in cAVS 1.5 IPC
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*
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* Secondary register, mapped to:
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* - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
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* - DIPCTE in cAVS 1.5 IPC
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*/
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/* Common bits in primary register */
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/* Reserved for doorbell */
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#define HDA_IPC_RSVD_31 BIT(31)
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/* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
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#define HDA_IPC_MSG_COMPACT BIT(30)
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/* Direction, 0 - request, 1 - response */
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#define HDA_IPC_RSP BIT(29)
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#define HDA_IPC_TYPE_SHIFT 24
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#define HDA_IPC_TYPE_MASK GENMASK(28, 24)
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#define HDA_IPC_TYPE(x) ((x) << HDA_IPC_TYPE_SHIFT)
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#define HDA_IPC_PM_GATE HDA_IPC_TYPE(0x8U)
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/* Command specific payload bits in secondary register */
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/* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */
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#define HDA_PM_NO_DMA_TRACE BIT(4)
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/* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
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#define HDA_PM_PCG BIT(3)
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/* Prevent power gating (0 - deep power state transitions allowed) */
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#define HDA_PM_PPG BIT(2)
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/* Indicates whether streaming is active */
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#define HDA_PM_PG_STREAMING BIT(1)
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#define HDA_PM_PG_RSVD BIT(0)
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irqreturn_t cnl_ipc_irq_thread(int irq, void *context);
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int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
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void cnl_ipc_dump(struct snd_sof_dev *sdev);
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#endif
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