/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip VAD driver
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*
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* Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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*/
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#ifndef _ROCKCHIP_VAD_H
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#define _ROCKCHIP_VAD_H
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#define VAD_CTRL 0x00
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#define VAD_DET_CHNL_SHIFT 29
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#define VAD_DET_CHNL_MASK GENMASK(31, 29)
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#define VAD_DET_CHNL(x) ((x) << VAD_DET_CHNL_SHIFT)
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#define AUDIO_24BIT_SAT_SHIFT 28
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#define AUDIO_24BIT_SAT_MASK BIT(28)
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#define AUDIO_H16B 0
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#define AUDIO_SAT_24TO16 BIT(28)
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#define AUDIO_24BIT_ALIGN_MODE_SHIFT 27
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#define AUDIO_24BIT_ALIGN_MODE_MASK BIT(27)
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#define AUDIO_24BIT_ALIGN_8_31B 0
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#define AUDIO_24BIT_ALIGN_0_23B BIT(27)
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#define AUDIO_CHNL_BW_SHIFT 26
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#define AUDIO_CHNL_BW_MASK BIT(26)
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#define AUDIO_CHNL_16B 0
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#define AUDIO_CHNL_24B BIT(26)
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#define AUDIO_CHNL_NUM_SHIFT 23
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#define AUDIO_CHNL_NUM_MASK GENMASK(25, 23)
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#define AUDIO_CHNL_NUM(x) ((x - 1) << AUDIO_CHNL_NUM_SHIFT)
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#define CFG_ACODE_AFTER_DET_EN_SHIFT 22
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#define CFG_ACODE_AFTER_DET_EN_MASK BIT(22)
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#define CFG_ACODE_AFTER_DET_EN BIT(22)
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#define VAD_MODE_SHIFT 20
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#define VAD_MODE_MASK GENMASK(21, 20)
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#define STORE_DATA_VAD_DET_ONLY 0
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#define STORE_DATA_ALL (1 << VAD_MODE_SHIFT)
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#define NO_STORE_DATA (2 << VAD_MODE_SHIFT)
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#define ACODE_CFG_REG_NUM_SHIFT 15
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#define ACODE_CFG_REG_NUM_MASK GENMASK(19, 15)
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#define ACODE_CFG_REG_NUM(x) ((x - 1) << ACODE_CFG_REG_NUM_SHIFT)
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#define SRC_ADDR_MODE_SHIFT 14
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#define SRC_ADDR_MODE_MASK BIT(14)
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#define SRC_ADDR_MODE_INC 0
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#define SRC_ADDR_MODE_FIXED BIT(14)
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#define INCR_BURST_LEN_SHIFT 10
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#define INCR_BURST_LEN_MASK GENMASK(13, 10)
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#define INCR_BURST_LEN(x) ((x - 1) << INCR_BURST_LEN_SHIFT)
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#define SRC_BURST_NUM_SHIFT 7
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#define SRC_BURST_NUM_MASK GENMASK(9, 7)
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#define SRC_BURST_NUM(x) ((x - 1) << SRC_BURST_NUM_SHIFT)
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#define SRC_BURST_SHIFT 4
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#define SRC_BURST_MASK GENMASK(6, 4)
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#define SRC_BURST_SIGNLE 0
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#define SRC_BURST_INCR (1 << SRC_BURST_SHIFT)
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#define SRC_BURST_INCR4 (3 << SRC_BURST_SHIFT)
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#define SRC_BURST_INCR8 (5 << SRC_BURST_SHIFT)
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#define SRC_BURST_INCR16 (7 << SRC_BURST_SHIFT)
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#define AUDIO_SRC_SEL_SHIFT 1
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#define AUDIO_SRC_SEL_MASK GENMASK(3, 1)
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#define AUDIO_SRC_SEL_I2S0 0
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#define AUDIO_SRC_SEL_I2S1 (1 << AUDIO_SRC_SEL_MASK)
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#define AUDIO_SRC_SEL_I2S2 (2 << AUDIO_SRC_SEL_MASK)
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#define AUDIO_SRC_SEL_I2S3 (3 << AUDIO_SRC_SEL_MASK)
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#define AUDIO_SRC_SEL_PDM (4 << AUDIO_SRC_SEL_MASK)
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#define VAD_EN_SHIFT 0
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#define VAD_EN_MASK BIT(0)
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#define VAD_EN BIT(0)
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#define VAD_DISABLE 0
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#define VAD_IS_ADDR 4
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#define VAD_ID_ADDR 8
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#define VAD_OD_ADDR0 0x0c
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#define VAD_OD_ADDR1 0x10
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#define VAD_OD_ADDR2 0x14
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#define VAD_OD_ADDR3 0x18
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#define VAD_OD_ADDR4 0x1c
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#define VAD_OD_ADDR5 0x20
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#define VAD_OD_ADDR6 0x24
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#define VAD_OD_ADDR7 0x28
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#define VAD_D_DATA0 0x2c
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#define VAD_D_DATA1 0x30
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#define VAD_D_DATA2 0x34
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#define VAD_D_DATA3 0x38
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#define VAD_D_DATA4 0x3c
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#define VAD_D_DATA5 0x40
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#define VAD_D_DATA6 0x44
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#define VAD_D_DATA7 0x48
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#define VAD_TIMEOUT 0x4c
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#define WORK_TIMEOUT_EN_MASK BIT(31)
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#define WORK_TIMEOUT_EN BIT(31)
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#define WORK_TIMEOUT_DISABLE 0
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#define IDLE_TIMEOUT_EN_MASK BIT(30)
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#define IDLE_TIMEOUT_EN BIT(30)
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#define IDLE_TIMEOUT_DISABLE 0
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#define WORK_TIMEOUT_THD_SHIFT 20
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#define WORK_TIMEOUT_THD_MASK GENMASK(29, 20)
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#define WORK_TIMEOUT_THD(x) ((x) << WORK_TIMEOUT_THD_SHIFT)
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#define IDLE_TIMEOUT_THD_SHIFT 0
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#define IDLE_TIMEOUT_THD_MASK GENMASK(19, 0)
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#define IDLE_TIMEOUT_THD(x) ((x) << IDLE_TIMEOUT_THD_SHIFT)
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#define VAD_RAM_BEGIN_ADDR 0x50
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#define VAD_RAM_END_ADDR 0x54
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#define VAD_RAM_CUR_ADDR 0x58
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#define VAD_DET_CON0 0x5c
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#define VAD_CON_THD_SHIFT 16
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#define VAD_CON_THD_MASK GENMASK(23, 16)
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#define VAD_CON_THD(x) ((x) << VAD_CON_THD_SHIFT)
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#define NOISE_LEVEL_SHIFT 12
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#define NOISE_LEVEL_MASK GENMASK(14, 12)
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#define NOISE_LEVEL(x) ((x) << NOISE_LEVEL_SHIFT)
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#define GAIN_SHIFT 0
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#define GAIN_MASK GENMASK(9, 0)
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#define GAIN(x) (x)
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#define VAD_DET_CON1 0x60
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#define MIN_NOISE_FIND_MODE_SHIFT 30
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#define MIN_NOISE_FIN_MODE_MASK BIT(30)
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#define MIN_NOISE_FIND_MODE0 0
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#define MIN_NOISE_FIND_MODE1 BIT(30)
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#define NOISE_CLEAN_MODE_SHIFT 29
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#define NOISE_CLEAN_MODE_MASK BIT(29)
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#define NOISE_CLEAN_MODE0 0
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#define NOISE_CLEAN_MODE1 BIT(29)
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#define NOISE_CLK_FORCE_EN_MASK BIT(28)
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#define NOISE_CLK_AUTO_GATING 0
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#define NOISE_CLK_FORCE_EN BIT(28)
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#define NOISE_SAMPLE_NUM_SHIFT 16
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#define NOISE_SAMPLE_NUM_MASK GENMASK(25, 16)
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#define NOISE_SAMPLE_NUM ((x) << NOISE_SAMPLE_NUM_SHIFT)
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#define SOUND_THD_MASK GENMASK(15, 0)
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#define SOUND_THD(x) (x)
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#define VAD_DET_CON2 0x64
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#define IIR_B0_SHIFT 16
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#define IIR_B0_MASK GENMASK(31, 16)
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#define IIR_B0(x) ((x) << IIR_B0_SHIFT)
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#define NOISE_ALPHA_SHIFT 8
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#define NOISE_ALPHA_MASK GENMASK(15, 8)
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#define NOISE_ALPHA(x) ((x) << NOISE_ALPHA_SHIFT)
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#define NOISE_FRM_NUM_MASK GENMASK(6, 0)
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#define NOISE_FRM_NUM(x) (x)
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#define VAD_DET_CON3 0x68
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#define IIR_B2_MASK GENMASK(31, 16)
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#define IIR_B2(x) ((x) << 16)
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#define IIR_B1_MASK GENMASK(15, 0)
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#define IIR_B1(x) (x)
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#define VAD_DET_CON4 0x6c
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#define IIR_A2_MASK GENMASK(31, 16)
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#define IIR_A2(x) ((x) << 16)
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#define IIR_A1_MASK GENMASK(15, 0)
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#define IIR_A1(x) (x)
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#define VAD_DET_CON5 0x70
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#define IIR_RESULT_SHIFT 16
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#define IIR_RESULT_MASK GENMASK(31, 16)
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#define NOISE_ABS_MASK GENMASK(15, 0)
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#define NOISE_ABS(x) (x)
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#define VAD_INT 0x74
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#define VAD_DATA_TRANS_INT_FLAG_MASK BIT(11)
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#define VAD_DATA_TRANS_INT_EN_MASK BIT(10)
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#define VAD_DATA_TRANS_INT_EN BIT(10)
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#define VAD_IDLE_MASK BIT(9)
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#define RAM_LOOP_FLGA_MASK BIT(8)
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#define WORK_TIMEOUT_FLAG_MASK BIT(7)
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#define IDLE_TIMEOUT_FLAG_MASK BIT(6)
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#define ERR_INT_FLAG_MASK BIT(5)
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#define VAD_DET_INT_FLAG_MASK BIT(4)
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#define WORK_TIMEOUT_INT_EN_MASK BIT(3)
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#define WORK_TIMEOUT_INT_EN BIT(3)
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#define IDLE_TIMEOUT_INT_EN_MASK BIT(2)
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#define IDLE_TIMEOUT_INT_EN BIT(2)
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#define ERR_INT_EN_MASK BIT(1)
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#define ERR_INT_EN BIT(1)
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#define VAD_DET_INT_EN_MASK BIT(0)
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#define VAD_DET_INT_EN BIT(0)
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#define VAD_AUX_CONTROL 0x78
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#define SAMPLE_CNT_EN_MASK BIT(29)
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#define SAMPLE_CNT_EN BIT(29)
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#define SAMPLE_CNT_DIS 0
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#define INT_TRIG_CTRL_EN_MASK BIT(28)
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#define INT_TRIG_CTRL_EN BIT(28)
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#define INT_TRIG_CTRL_DIS 0
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#define INT_TRIG_VALID_THD_MASK GENMASK(27, 16)
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#define INT_TRIG_VALID_THD(x) (((x) - 1) << 16)
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#define DATA_TRANS_KBYTE_THD_MASK GENMASK(11, 4)
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#define DATA_TRANS_KBYTE_THD(x) (((x) - 1) << 4)
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#define DATA_TRANS_TRIG_INT_EN_MASK BIT(2)
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#define DATA_TRANS_TRIG_INT_EN BIT(2)
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#define DATA_TRANS_TRIG_INT_DIS 0
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#define RAM_ITF_EN_MASK BIT(1)
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#define RAM_ITF_EN 0
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#define RAM_ITF_DIS BIT(1)
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#define BUS_WRITE_EN_MASK BIT(0)
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#define BUS_WRITE_EN BIT(0)
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#define BUS_WRITE_DIS 0
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#define VAD_SAMPLE_CNT 0x7c
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#define VAD_NOISE_DATA 0x100
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/* RK1808 SOC */
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#define RK1808_I2S0 0xff7e0800
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#define RK1808_I2S1 0xff7f0800
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#define RK1808_PDM 0xff800400
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/* RK3308 SOC */
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#define ACODEC_BASE 0xff560000
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#define ACODEC_ADC_ANA_CON0 0X340
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#define RK3308_I2S_8CH_0 0xff300800
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#define RK3308_I2S_8CH_1 0xff310800
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#define RK3308_I2S_8CH_2 0xff320800
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#define RK3308_I2S_8CH_3 0xff330800
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#define RK3308_PDM_8CH 0xff380400
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/* RK3568 SOC */
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#define RK3568_I2S_8CH_1 0xfe410800
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#define RK3568_I2S_2CH_2 0xfe420800
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#define RK3568_I2S_2CH_3 0xfe430800
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#define RK3568_PDM 0xfe440400
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/* RK3588 SOC */
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#define RK3588_I2S1_8CH 0xfe480800
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#define RK3588_PDM0 0xfe4b0400
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#endif
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